SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1178272 | 1 | T11 | 3 | T12 | 1 | T13 | 2 | ||||
auto[1] | 184230 | 1 | T58 | 80 | T59 | 80 | T54 | 3354 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1362296 | 1 | T11 | 3 | T12 | 1 | T13 | 2 | ||||
values[1] | 24 | 1 | T180 | 1 | T181 | 1 | T209 | 2 | ||||
values[2] | 4 | 1 | T179 | 1 | T210 | 1 | T211 | 1 | ||||
values[3] | 93 | 1 | T179 | 4 | T180 | 8 | T181 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 1362290 | 1 | T11 | 3 | T12 | 1 | T13 | 2 | ||||
values[1] | 24 | 1 | T179 | 3 | T180 | 2 | T209 | 2 | ||||
values[2] | 2 | 1 | T181 | 1 | T212 | 1 | - | - | ||||
values[3] | 112 | 1 | T179 | 7 | T180 | 6 | T181 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 1362192 | 1 | T11 | 3 | T12 | 1 | T13 | 2 | ||||
auto[TlIntgErrCmd] | 98 | 1 | T179 | 3 | T180 | 6 | T181 | 6 | ||||
auto[TlIntgErrData] | 104 | 1 | T179 | 9 | T180 | 4 | T181 | 1 | ||||
auto[TlIntgErrBoth] | 108 | 1 | T179 | 8 | T180 | 10 | T181 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 317659 | 0 | T1 | 1 | T2 | 1 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 317446 | 1 | T1 | 1 | T2 | 1 | T3 | 5 | ||||
values[1] | 17 | 1 | T179 | 3 | T181 | 1 | T213 | 1 | ||||
values[2] | 3 | 1 | T213 | 1 | T214 | 1 | T215 | 1 | ||||
values[3] | 111 | 1 | T179 | 8 | T180 | 8 | T181 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 317473 | 1 | T1 | 1 | T2 | 1 | T3 | 5 | ||||
values[1] | 17 | 1 | T179 | 2 | T180 | 1 | T216 | 1 | ||||
values[2] | 8 | 1 | T179 | 2 | T180 | 1 | T211 | 1 | ||||
values[3] | 97 | 1 | T179 | 6 | T180 | 8 | T181 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 317349 | 1 | T1 | 1 | T2 | 1 | T3 | 5 | ||||
auto[TlIntgErrCmd] | 124 | 1 | T179 | 7 | T180 | 8 | T181 | 3 | ||||
auto[TlIntgErrData] | 97 | 1 | T179 | 7 | T180 | 6 | T181 | 3 | ||||
auto[TlIntgErrBoth] | 89 | 1 | T179 | 6 | T180 | 6 | T181 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |