Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

727835

1

T11

3

T12

1

T13

1

full_word

634667

1

T13

1

T14

2

T15

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1362192	1			T11	3		T12	1		T13	2
auto[TlIntgErrCmd]	98	1			T179	3		T180	6		T181	6
auto[TlIntgErrData]	104	1			T179	9		T180	4		T181	1
auto[TlIntgErrBoth]	108	1			T179	8		T180	10		T181	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

529123

1

T14

1

T15

1

T42

3

auto[1]

833379

1

T11

3

T12

1

T13

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	219604	1			T15	1		T55	5		T43	4
auto[TlIntgErrNone]	partial	auto[1]	507951	1			T11	3		T12	1		T13	1
auto[TlIntgErrNone]	full_word	auto[0]	309381	1			T14	1		T42	3		T55	5
auto[TlIntgErrNone]	full_word	auto[1]	325256	1			T13	1		T14	1		T15	1
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T179	1		T180	5		T181	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T179	2		T180	1		T181	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T217	1		T218	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T181	1		T216	1		T219	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T179	3		T180	2		T209	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T179	6		T180	1		T181	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T180	1		T209	1		T216	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T220	1		T211	1		T221	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T179	3		T180	5		T181	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T179	5		T180	4		T181	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T180	1		T213	1		T211	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T181	1		T213	1		T217	1