Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	132344115	144951	0	0
late_debug_enable_rd_A	132344115	14090	0	0
late_debug_enable_regwen_rd_A	132344115	12740	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132344115	144951	0	0
T9	0	3999	0	0
T17	0	5834	0	0
T26	322492	0	0	0
T34	0	10380	0	0
T38	0	7039	0	0
T54	68417	2599	0	0
T60	8045	0	0	0
T62	0	5496	0	0
T74	0	7237	0	0
T89	274794	0	0	0
T105	0	13829	0	0
T108	0	2360	0	0
T112	0	11049	0	0
T113	571747	0	0	0
T114	7190	0	0	0
T115	421164	0	0	0
T116	526187	0	0	0
T117	2507	0	0	0
T118	62986	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132344115	14090	0	0
T9	178602	1108	0	0
T74	0	2566	0	0
T106	0	42	0	0
T107	0	16	0	0
T112	0	1941	0	0
T124	0	8	0	0
T142	0	5	0	0
T166	0	2	0	0
T167	0	219	0	0
T168	0	17	0	0
T169	3156	0	0	0
T170	885678	0	0	0
T171	300256	0	0	0
T172	64901	0	0	0
T173	1956	0	0	0
T174	117888	0	0	0
T175	788511	0	0	0
T176	158290	0	0	0
T177	70970	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132344115	12740	0	0
T9	178602	945	0	0
T74	0	2219	0	0
T106	0	48	0	0
T107	0	7	0	0
T112	0	1754	0	0
T124	0	5	0	0
T140	0	3	0	0
T166	0	2	0	0
T167	0	199	0	0
T168	0	14	0	0
T169	3156	0	0	0
T170	885678	0	0	0
T171	300256	0	0	0
T172	64901	0	0	0
T173	1956	0	0	0
T174	117888	0	0	0
T175	788511	0	0	0
T176	158290	0	0	0
T177	70970	0	0	0