Unified Coverage Report :: Module :: prim_secded_inv_39_32_dec

Module : prim_secded_inv_39_32_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk	100.00			100.00
tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk	100.00			100.00
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						gen_rsp_data_intg_check.u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_39_32_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
data_o[31:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T45,T44	Yes	T2,T3,T44	OUTPUT
err_o[1:0]	Yes	Yes	T3,T11,T45	Yes	T3,T12,T13	OUTPUT

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T45,T44,T22	Yes	T45,T44,T58	INPUT
data_o[31:0]	Yes	Yes	T45,T44,T22	Yes	T45,T44,T58	OUTPUT
syndrome_o[6:0]	Yes	Yes	T45,T44,T58	Yes	T44,T43,T67	OUTPUT
err_o[1:0]	Yes	Yes	T45,T44,T43	Yes	T45,T58,T43	OUTPUT

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T20	INPUT
data_o[31:0]	Yes	Yes	T2,T3,T13	Yes	T2,T3,T20	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T21,T22	Yes	T3,T21,T22	OUTPUT
err_o[1:0]	Yes	Yes	T3,T20,T21	Yes	T3,T13,T20	OUTPUT

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T12,T14,T15	Yes	T12,T13,T14	INPUT
data_o[31:0]	Yes	Yes	T12,T14,T15	Yes	T12,T13,T14	OUTPUT
syndrome_o[6:0]	Yes	Yes	T5,T68,T32	Yes	T2,T12,T5	OUTPUT
err_o[1:0]	Yes	Yes	T11,T12,T13	Yes	T12,T15,T5	OUTPUT