Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT97

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT97
11CoveredT97

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT97
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8404925 8403433 0 0
selKnown1 63430352 63428860 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8404925 8403433 0 0
T1 6116 6114 0 0
T2 31776 31774 0 0
T3 38981 38977 0 0
T4 2764 2760 0 0
T6 0 2 0 0
T7 0 1 0 0
T11 2950 2946 0 0
T12 1940 1936 0 0
T13 1988 1984 0 0
T14 1640 1636 0 0
T15 2 0 0 0
T20 19336 19332 0 0
T22 0 10 0 0
T23 0 8 0 0
T25 0 2 0 0
T30 0 9 0 0
T44 2 0 0 0
T45 650 646 0 0
T67 0 2 0 0
T68 0 40 0 0
T87 0 5 0 0
T97 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 63430352 63428860 0 0
T1 165502 165500 0 0
T2 102785 102783 0 0
T3 440667 440663 0 0
T4 11458 11454 0 0
T11 16695 16691 0 0
T12 19079 19075 0 0
T13 10229 10225 0 0
T14 8875 8871 0 0
T15 2 0 0 0
T20 272159 272155 0 0
T22 0 10 0 0
T23 0 16 0 0
T30 0 6 0 0
T44 2 0 0 0
T45 11143 11139 0 0
T67 0 2 0 0
T68 0 40 0 0
T69 0 2 0 0
T81 0 40 0 0
T87 0 10 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT97

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT97
11CoveredT97

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT97
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2750951 2750688 0 0
selKnown1 57776491 57776228 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2750951 2750688 0 0
T1 3058 3057 0 0
T2 15888 15887 0 0
T3 19485 19484 0 0
T4 1381 1380 0 0
T11 1474 1473 0 0
T12 969 968 0 0
T13 993 992 0 0
T14 819 818 0 0
T20 9663 9662 0 0
T45 324 323 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 57776491 57776228 0 0
T1 162444 162443 0 0
T2 86897 86896 0 0
T3 421172 421171 0 0
T4 10075 10074 0 0
T11 15219 15218 0 0
T12 18108 18107 0 0
T13 9234 9233 0 0
T14 8054 8053 0 0
T20 262486 262485 0 0
T45 10817 10816 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT97

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT97
11CoveredT97

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT97
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 792 529 0 0
selKnown1 746 483 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 792 529 0 0
T3 5 4 0 0
T4 1 0 0 0
T6 0 1 0 0
T11 1 0 0 0
T12 1 0 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 1 0 0 0
T20 5 4 0 0
T22 0 5 0 0
T23 0 8 0 0
T25 0 1 0 0
T30 0 4 0 0
T44 1 0 0 0
T45 1 0 0 0
T67 0 1 0 0
T68 0 20 0 0
T87 0 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 746 483 0 0
T3 5 4 0 0
T4 1 0 0 0
T11 1 0 0 0
T12 1 0 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 1 0 0 0
T20 5 4 0 0
T22 0 5 0 0
T23 0 8 0 0
T30 0 3 0 0
T44 1 0 0 0
T45 1 0 0 0
T67 0 1 0 0
T68 0 20 0 0
T69 0 1 0 0
T81 0 20 0 0
T87 0 5 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT97

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT97
11CoveredT97

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT97
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 5651381 5650898 0 0
selKnown1 5651381 5650898 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 5651381 5650898 0 0
T1 3058 3057 0 0
T2 15888 15887 0 0
T3 19485 19484 0 0
T4 1381 1380 0 0
T11 1474 1473 0 0
T12 969 968 0 0
T13 993 992 0 0
T14 819 818 0 0
T20 9663 9662 0 0
T45 324 323 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 5651381 5650898 0 0
T1 3058 3057 0 0
T2 15888 15887 0 0
T3 19485 19484 0 0
T4 1381 1380 0 0
T11 1474 1473 0 0
T12 969 968 0 0
T13 993 992 0 0
T14 819 818 0 0
T20 9663 9662 0 0
T45 324 323 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT97

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT97
11CoveredT97

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT97
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1801 1318 0 0
selKnown1 1734 1251 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1801 1318 0 0
T3 6 5 0 0
T4 1 0 0 0
T6 0 1 0 0
T7 0 1 0 0
T11 1 0 0 0
T12 1 0 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 1 0 0 0
T20 5 4 0 0
T22 0 5 0 0
T25 0 1 0 0
T30 0 5 0 0
T44 1 0 0 0
T45 1 0 0 0
T67 0 1 0 0
T68 0 20 0 0
T97 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1734 1251 0 0
T3 5 4 0 0
T4 1 0 0 0
T11 1 0 0 0
T12 1 0 0 0
T13 1 0 0 0
T14 1 0 0 0
T15 1 0 0 0
T20 5 4 0 0
T22 0 5 0 0
T23 0 8 0 0
T30 0 3 0 0
T44 1 0 0 0
T45 1 0 0 0
T67 0 1 0 0
T68 0 20 0 0
T69 0 1 0 0
T81 0 20 0 0
T87 0 5 0 0

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