Unified Coverage Report :: Module :: tlul_err_resp

Module : tlul_err_resp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp	100.00	100.00	100.00			100.00
tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.91	86.27	76.47		100.00	81.82	50.00	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.00	100.00	100.00		100.00	100.00	50.00	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

Line Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	65	1	1	100.00

33                        always_ff @(posedge clk_i or negedge rst_ni) begin
34         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
35         1/1                err_rsp_pending <= 1'b0;
           Tests:       T1 T2 T3 
36         1/1                err_source      <= {top_pkg::TL_AIW{1'b0}};
           Tests:       T1 T2 T3 
37         1/1                err_opcode      <= Get;
           Tests:       T1 T2 T3 
38         1/1                err_size        <= '0;
           Tests:       T1 T2 T3 
39         1/1                err_instr_type  <= MuBi4False;
           Tests:       T1 T2 T3 
40         1/1              end else if (err_rsp_pending && tl_h_i.d_ready) begin
           Tests:       T1 T2 T3 
41         1/1                err_rsp_pending <= 1'b0;
           Tests:       T83 T41 T76 
42         1/1              end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
           Tests:       T1 T2 T3 
43         1/1                err_rsp_pending <= 1'b1;
           Tests:       T83 T41 T76 
44         1/1                err_source      <= tl_h_i.a_source;
           Tests:       T83 T41 T76 
45         1/1                err_opcode      <= tl_h_i.a_opcode;
           Tests:       T83 T41 T76 
46         1/1                err_size        <= tl_h_i.a_size;
           Tests:       T83 T41 T76 
47         1/1                err_instr_type  <= tl_h_i.a_user.instr_type;
           Tests:       T83 T41 T76 
48                          end
                        MISSING_ELSE
49                        end
50                      
51         1/1            assign tl_h_o_int.a_ready  = ~err_rsp_pending;
           Tests:       T1 T2 T3 
52         1/1            assign tl_h_o_int.d_valid  = err_rsp_pending;
           Tests:       T1 T2 T3 
53         1/1            assign tl_h_o_int.d_data   = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
           Tests:       T1 T2 T3 
54                                                                                                DataWhenError;
55         1/1            assign tl_h_o_int.d_source = err_source;
           Tests:       T1 T2 T3 
56                        assign tl_h_o_int.d_sink   = '0;
57                        assign tl_h_o_int.d_param  = '0;
58         1/1            assign tl_h_o_int.d_size   = err_size;
           Tests:       T1 T2 T3 
59         1/1            assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
           Tests:       T1 T2 T3 
60                        assign tl_h_o_int.d_user   = '0;
61                        assign tl_h_o_int.d_error  = 1'b1;
62                      
63                        // Waive unused bits of tl_h_i
64                        logic unused_tl_h;
65         1/1            assign unused_tl_h = ^tl_h_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : tlul_err_resp

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T76,T17,T9
1	1	Covered	T83,T41,T76

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T9,T74
1	1	Covered	T83,T41,T76

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T83,T41,T178
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00

59           assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T83,T41,T178

34             if (!rst_ni) begin
               -1-  
35               err_rsp_pending <= 1'b0;
                 ==>
36               err_source      <= {top_pkg::TL_AIW{1'b0}};
37               err_opcode      <= Get;
38               err_size        <= '0;
39               err_instr_type  <= MuBi4False;
40             end else if (err_rsp_pending && tl_h_i.d_ready) begin
                        -2-  
41               err_rsp_pending <= 1'b0;
                 ==>
42             end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
                        -3-  
43               err_rsp_pending <= 1'b1;
                 ==>
44               err_source      <= tl_h_i.a_source;
45               err_opcode      <= tl_h_i.a_opcode;
46               err_size        <= tl_h_i.a_size;
47               err_instr_type  <= tl_h_i.a_user.instr_type;
48             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T83,T41,T76
0	0	1	Covered	T83,T41,T76
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	65	1	1	100.00

33                        always_ff @(posedge clk_i or negedge rst_ni) begin
34         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
35         1/1                err_rsp_pending <= 1'b0;
           Tests:       T1 T2 T3 
36         1/1                err_source      <= {top_pkg::TL_AIW{1'b0}};
           Tests:       T1 T2 T3 
37         1/1                err_opcode      <= Get;
           Tests:       T1 T2 T3 
38         1/1                err_size        <= '0;
           Tests:       T1 T2 T3 
39         1/1                err_instr_type  <= MuBi4False;
           Tests:       T1 T2 T3 
40         1/1              end else if (err_rsp_pending && tl_h_i.d_ready) begin
           Tests:       T1 T2 T3 
41         1/1                err_rsp_pending <= 1'b0;
           Tests:       T41 T76 T178 
42         1/1              end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
           Tests:       T1 T2 T3 
43         1/1                err_rsp_pending <= 1'b1;
           Tests:       T41 T76 T178 
44         1/1                err_source      <= tl_h_i.a_source;
           Tests:       T41 T76 T178 
45         1/1                err_opcode      <= tl_h_i.a_opcode;
           Tests:       T41 T76 T178 
46         1/1                err_size        <= tl_h_i.a_size;
           Tests:       T41 T76 T178 
47         1/1                err_instr_type  <= tl_h_i.a_user.instr_type;
           Tests:       T41 T76 T178 
48                          end
                        MISSING_ELSE
49                        end
50                      
51         1/1            assign tl_h_o_int.a_ready  = ~err_rsp_pending;
           Tests:       T1 T2 T3 
52         1/1            assign tl_h_o_int.d_valid  = err_rsp_pending;
           Tests:       T1 T2 T3 
53         1/1            assign tl_h_o_int.d_data   = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
           Tests:       T1 T2 T3 
54                                                                                                DataWhenError;
55         1/1            assign tl_h_o_int.d_source = err_source;
           Tests:       T1 T2 T3 
56                        assign tl_h_o_int.d_sink   = '0;
57                        assign tl_h_o_int.d_param  = '0;
58         1/1            assign tl_h_o_int.d_size   = err_size;
           Tests:       T1 T2 T3 
59         1/1            assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
           Tests:       T1 T2 T3 
60                        assign tl_h_o_int.d_user   = '0;
61                        assign tl_h_o_int.d_error  = 1'b1;
62                      
63                        // Waive unused bits of tl_h_i
64                        logic unused_tl_h;
65         1/1            assign unused_tl_h = ^tl_h_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T41,T76,T178

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T41,T76,T178

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T41,T178
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00

59           assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T41,T178

34             if (!rst_ni) begin
               -1-  
35               err_rsp_pending <= 1'b0;
                 ==>
36               err_source      <= {top_pkg::TL_AIW{1'b0}};
37               err_opcode      <= Get;
38               err_size        <= '0;
39               err_instr_type  <= MuBi4False;
40             end else if (err_rsp_pending && tl_h_i.d_ready) begin
                        -2-  
41               err_rsp_pending <= 1'b0;
                 ==>
42             end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
                        -3-  
43               err_rsp_pending <= 1'b1;
                 ==>
44               err_source      <= tl_h_i.a_source;
45               err_opcode      <= tl_h_i.a_opcode;
46               err_size        <= tl_h_i.a_size;
47               err_instr_type  <= tl_h_i.a_user.instr_type;
48             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T41,T76,T178
0	0	1	Covered	T41,T76,T178
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	65	1	1	100.00

33                        always_ff @(posedge clk_i or negedge rst_ni) begin
34         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
35         1/1                err_rsp_pending <= 1'b0;
           Tests:       T1 T2 T3 
36         1/1                err_source      <= {top_pkg::TL_AIW{1'b0}};
           Tests:       T1 T2 T3 
37         1/1                err_opcode      <= Get;
           Tests:       T1 T2 T3 
38         1/1                err_size        <= '0;
           Tests:       T1 T2 T3 
39         1/1                err_instr_type  <= MuBi4False;
           Tests:       T1 T2 T3 
40         1/1              end else if (err_rsp_pending && tl_h_i.d_ready) begin
           Tests:       T1 T2 T3 
41         1/1                err_rsp_pending <= 1'b0;
           Tests:       T83 T76 T79 
42         1/1              end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
           Tests:       T1 T2 T3 
43         1/1                err_rsp_pending <= 1'b1;
           Tests:       T83 T76 T79 
44         1/1                err_source      <= tl_h_i.a_source;
           Tests:       T83 T76 T79 
45         1/1                err_opcode      <= tl_h_i.a_opcode;
           Tests:       T83 T76 T79 
46         1/1                err_size        <= tl_h_i.a_size;
           Tests:       T83 T76 T79 
47         1/1                err_instr_type  <= tl_h_i.a_user.instr_type;
           Tests:       T83 T76 T79 
48                          end
                        MISSING_ELSE
49                        end
50                      
51         1/1            assign tl_h_o_int.a_ready  = ~err_rsp_pending;
           Tests:       T1 T2 T3 
52         1/1            assign tl_h_o_int.d_valid  = err_rsp_pending;
           Tests:       T1 T2 T3 
53         1/1            assign tl_h_o_int.d_data   = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError :
           Tests:       T1 T2 T3 
54                                                                                                DataWhenError;
55         1/1            assign tl_h_o_int.d_source = err_source;
           Tests:       T1 T2 T3 
56                        assign tl_h_o_int.d_sink   = '0;
57                        assign tl_h_o_int.d_param  = '0;
58         1/1            assign tl_h_o_int.d_size   = err_size;
           Tests:       T1 T2 T3 
59         1/1            assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
           Tests:       T1 T2 T3 
60                        assign tl_h_o_int.d_user   = '0;
61                        assign tl_h_o_int.d_error  = 1'b1;
62                      
63                        // Waive unused bits of tl_h_i
64                        logic unused_tl_h;
65         1/1            assign unused_tl_h = ^tl_h_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T76,T17,T9
1	1	Covered	T83,T76,T79

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T9,T74
1	1	Covered	T83,T76,T79

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T83,T79,T17
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00

59           assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
                                                              -1-  
                                                              ==>  
                                                              ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T83,T79,T17

34             if (!rst_ni) begin
               -1-  
35               err_rsp_pending <= 1'b0;
                 ==>
36               err_source      <= {top_pkg::TL_AIW{1'b0}};
37               err_opcode      <= Get;
38               err_size        <= '0;
39               err_instr_type  <= MuBi4False;
40             end else if (err_rsp_pending && tl_h_i.d_ready) begin
                        -2-  
41               err_rsp_pending <= 1'b0;
                 ==>
42             end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin
                        -3-  
43               err_rsp_pending <= 1'b1;
                 ==>
44               err_source      <= tl_h_i.a_source;
45               err_opcode      <= tl_h_i.a_opcode;
46               err_size        <= tl_h_i.a_size;
47               err_instr_type  <= tl_h_i.a_user.instr_type;
48             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T83,T76,T79
0	0	1	Covered	T83,T76,T79
0	0	0	Covered	T1,T2,T3