Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	60.77			60.77
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.77			60.77

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.77			60.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T3,*T12	Yes	T2,T3,T45	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T2,T3,T45	Yes	T2,T3,T11	INPUT
data_o[56:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T45	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T12,T20	Yes	T3,T12,T45	OUTPUT
err_o[1:0]	Yes	Yes	T3,T11,T45	Yes	T3,T13,T45	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	158	60.77
Total Bits 0->1	130	79	60.77
Total Bits 1->0	130	79	60.77

Ports	4	3	75.00
Port Bits	260	158	60.77
Port Bits 0->1	130	79	60.77
Port Bits 1->0	130	79	60.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[5:0]	Yes	Yes	*T2,*T3,*T13	Yes	T3,T20,T21	INPUT
data_i[56:6]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T2,T3,T20	Yes	T2,T3,T13	INPUT
data_o[56:0]	Yes	Yes	T2,T3,T13	Yes	T3,T20,T21	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T20,T21	Yes	T3,T20,T21	OUTPUT
err_o[1:0]	Yes	Yes	T3,T20,T21	Yes	T3,T13,T20	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T45,*T44,*T43	Yes	T45,T44,T58	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T3,T45,T22	Yes	T3,T45,T22	INPUT
data_o[56:0]	Yes	Yes	T45,T44,T43	Yes	T45,T44,T58	OUTPUT
syndrome_o[6:0]	Yes	Yes	T44,T43,T67	Yes	T45,T67,T68	OUTPUT
err_o[1:0]	Yes	Yes	T45,T44,T58	Yes	T45,T44,T43	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T12,*T15,*T5	Yes	T2,T11,T12	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T15,T5,T42	Yes	T2,T11,T14	INPUT
data_o[56:0]	Yes	Yes	T12,T15,T5	Yes	T2,T11,T12	OUTPUT
syndrome_o[6:0]	Yes	Yes	T12,T5,T68	Yes	T12,T45,T5	OUTPUT
err_o[1:0]	Yes	Yes	T11,T12,T13	Yes	T15,T5,T76	OUTPUT

*Tests covering at least one bit in the range