Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	292416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

596509

1

T6

2

T13

2

T28

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	546303	1			T28	1		T14	1		T42	3
values[0x0]	145176	1			T6	1		T12	1		T13	1
values[0x1]	197446	1			T3	1		T6	1		T13	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196192	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

692733

1

T3

1

T6

2

T13

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3977	1			T68	16		T50	27		T177	2
valid_sources[0x01]	3381	1			T68	25		T80	1		T50	40
valid_sources[0x02]	3806	1			T68	18		T50	29		T37	43
valid_sources[0x03]	3111	1			T71	2		T68	16		T50	25
valid_sources[0x04]	3894	1			T71	1		T68	13		T50	26
valid_sources[0x05]	3658	1			T17	1		T68	21		T50	33
valid_sources[0x06]	3392	1			T68	26		T50	32		T177	2
valid_sources[0x07]	4432	1			T68	12		T218	1		T219	21
valid_sources[0x08]	3440	1			T68	18		T50	39		T37	31
valid_sources[0x09]	3205	1			T72	4		T68	27		T50	21
valid_sources[0x0a]	3407	1			T71	2		T68	16		T50	20
valid_sources[0x0b]	3258	1			T69	1		T68	12		T50	35
valid_sources[0x0c]	3568	1			T68	22		T50	25		T37	34
valid_sources[0x0d]	3475	1			T32	2		T68	24		T80	1
valid_sources[0x0e]	4691	1			T68	19		T50	36		T37	40
valid_sources[0x0f]	3099	1			T68	15		T79	19		T50	25
valid_sources[0x10]	3093	1			T71	1		T68	14		T34	5
valid_sources[0x11]	2944	1			T42	7		T68	12		T50	38
valid_sources[0x12]	3551	1			T68	19		T50	25		T37	27
valid_sources[0x13]	3103	1			T69	1		T68	17		T206	1
valid_sources[0x14]	3244	1			T68	15		T50	27		T220	5
valid_sources[0x15]	3090	1			T68	20		T207	1		T50	37
valid_sources[0x16]	3554	1			T68	16		T50	21		T37	26
valid_sources[0x17]	3481	1			T68	12		T50	33		T37	50
valid_sources[0x18]	3383	1			T68	27		T50	52		T37	60
valid_sources[0x19]	3406	1			T68	26		T50	27		T220	1
valid_sources[0x1a]	3135	1			T14	1		T71	1		T68	10
valid_sources[0x1b]	4023	1			T204	1		T68	15		T122	6
valid_sources[0x1c]	3757	1			T68	9		T50	28		T37	22
valid_sources[0x1d]	4068	1			T68	16		T50	47		T37	34
valid_sources[0x1e]	2854	1			T68	21		T50	28		T37	28
valid_sources[0x1f]	3252	1			T68	14		T195	5		T50	30
valid_sources[0x20]	3005	1			T71	1		T68	21		T50	35
valid_sources[0x21]	3476	1			T68	14		T50	32		T37	29
valid_sources[0x22]	3497	1			T71	1		T17	1		T221	2
valid_sources[0x23]	3093	1			T13	1		T78	5		T68	19
valid_sources[0x24]	3223	1			T71	3		T68	19		T50	39
valid_sources[0x25]	3299	1			T71	2		T173	1		T68	23
valid_sources[0x26]	3597	1			T68	17		T50	39		T37	24
valid_sources[0x27]	3206	1			T68	7		T50	45		T37	31
valid_sources[0x28]	3215	1			T61	1		T68	15		T218	1
valid_sources[0x29]	3082	1			T60	1		T68	21		T50	24
valid_sources[0x2a]	3005	1			T71	2		T68	23		T50	45
valid_sources[0x2b]	3068	1			T63	1		T203	1		T68	20
valid_sources[0x2c]	3242	1			T72	2		T68	23		T50	32
valid_sources[0x2d]	4484	1			T68	21		T50	22		T37	29
valid_sources[0x2e]	3212	1			T71	2		T17	1		T68	23
valid_sources[0x2f]	4160	1			T68	19		T50	44		T37	23
valid_sources[0x30]	3846	1			T68	20		T50	34		T179	1
valid_sources[0x31]	3515	1			T71	1		T77	17		T68	22
valid_sources[0x32]	3274	1			T97	1		T190	1		T68	17
valid_sources[0x33]	3380	1			T71	1		T63	2		T68	25
valid_sources[0x34]	3686	1			T55	2		T73	1		T68	20
valid_sources[0x35]	3396	1			T68	14		T206	1		T50	41
valid_sources[0x36]	3059	1			T68	13		T50	24		T37	30
valid_sources[0x37]	3452	1			T69	4		T68	20		T50	49
valid_sources[0x38]	3555	1			T68	13		T50	46		T37	31
valid_sources[0x39]	3535	1			T13	2		T71	1		T193	1
valid_sources[0x3a]	3156	1			T71	1		T68	21		T218	1
valid_sources[0x3b]	3266	1			T59	2		T68	17		T50	42
valid_sources[0x3c]	3384	1			T71	1		T68	25		T50	27
valid_sources[0x3d]	3564	1			T3	1		T71	1		T68	14
valid_sources[0x3e]	4025	1			T68	18		T50	44		T37	25
valid_sources[0x3f]	3163	1			T71	1		T68	14		T80	1
valid_sources[0x40]	3531	1			T71	1		T39	1		T68	23
valid_sources[0x41]	3670	1			T71	1		T142	1		T17	1
valid_sources[0x42]	3445	1			T68	16		T50	53		T37	10
valid_sources[0x43]	3624	1			T68	23		T50	43		T37	21
valid_sources[0x44]	3957	1			T74	7		T68	10		T40	2
valid_sources[0x45]	3336	1			T68	19		T50	22		T37	14
valid_sources[0x46]	4847	1			T68	10		T50	51		T184	1
valid_sources[0x47]	3379	1			T68	22		T50	37		T37	54
valid_sources[0x48]	3695	1			T71	1		T68	15		T50	31
valid_sources[0x49]	3592	1			T204	1		T68	15		T50	33
valid_sources[0x4a]	3443	1			T68	19		T50	30		T37	40
valid_sources[0x4b]	3427	1			T72	23		T68	20		T50	43
valid_sources[0x4c]	3366	1			T6	1		T17	1		T68	22
valid_sources[0x4d]	3341	1			T39	1		T68	23		T50	47
valid_sources[0x4e]	3354	1			T39	1		T68	18		T50	47
valid_sources[0x4f]	3564	1			T78	2		T68	13		T80	1
valid_sources[0x50]	3688	1			T73	1		T68	28		T50	39
valid_sources[0x51]	3257	1			T31	1		T68	20		T50	30
valid_sources[0x52]	3173	1			T39	2		T68	26		T40	1
valid_sources[0x53]	3458	1			T68	22		T50	19		T37	24
valid_sources[0x54]	3214	1			T72	2		T63	1		T68	15
valid_sources[0x55]	3297	1			T72	2		T193	2		T68	24
valid_sources[0x56]	3569	1			T89	2		T68	34		T50	36
valid_sources[0x57]	3053	1			T70	2		T26	4		T68	18
valid_sources[0x58]	3382	1			T68	7		T50	19		T37	26
valid_sources[0x59]	3448	1			T68	20		T50	29		T36	3
valid_sources[0x5a]	4863	1			T68	23		T50	33		T37	26
valid_sources[0x5b]	3635	1			T143	2		T68	18		T50	33
valid_sources[0x5c]	3428	1			T71	2		T68	23		T222	4
valid_sources[0x5d]	3371	1			T71	2		T203	1		T68	18
valid_sources[0x5e]	3285	1			T68	25		T207	2		T223	1
valid_sources[0x5f]	3599	1			T70	4		T199	1		T68	16
valid_sources[0x60]	3474	1			T69	2		T68	24		T50	37
valid_sources[0x61]	3830	1			T31	1		T68	12		T50	32
valid_sources[0x62]	3157	1			T68	17		T50	56		T37	22
valid_sources[0x63]	3460	1			T60	1		T68	18		T65	18
valid_sources[0x64]	3146	1			T72	5		T17	1		T68	17
valid_sources[0x65]	3639	1			T68	21		T50	53		T37	38
valid_sources[0x66]	3459	1			T68	22		T195	8		T223	1
valid_sources[0x67]	3270	1			T72	3		T199	1		T68	21
valid_sources[0x68]	3495	1			T71	2		T27	9		T68	28
valid_sources[0x69]	4136	1			T69	1		T71	1		T68	21
valid_sources[0x6a]	3604	1			T71	1		T61	4		T68	19
valid_sources[0x6b]	2963	1			T39	1		T68	19		T50	50
valid_sources[0x6c]	3448	1			T173	1		T39	1		T68	19
valid_sources[0x6d]	2565	1			T68	19		T50	14		T37	34
valid_sources[0x6e]	3199	1			T68	17		T50	35		T37	33
valid_sources[0x6f]	3634	1			T52	2		T68	21		T50	23
valid_sources[0x70]	3837	1			T68	19		T50	34		T37	26
valid_sources[0x71]	3914	1			T224	3		T68	16		T50	24
valid_sources[0x72]	3365	1			T68	21		T50	33		T37	20
valid_sources[0x73]	3290	1			T61	2		T73	1		T225	1
valid_sources[0x74]	3491	1			T68	24		T80	1		T50	33
valid_sources[0x75]	3114	1			T60	2		T68	19		T50	30
valid_sources[0x76]	3085	1			T68	20		T50	57		T37	41
valid_sources[0x77]	3015	1			T68	27		T207	2		T50	44
valid_sources[0x78]	3414	1			T68	14		T80	1		T50	43
valid_sources[0x79]	3590	1			T71	1		T68	17		T50	32
valid_sources[0x7a]	3423	1			T63	1		T68	15		T80	1
valid_sources[0x7b]	4844	1			T71	1		T68	21		T50	43
valid_sources[0x7c]	3487	1			T68	14		T50	37		T37	26
valid_sources[0x7d]	3062	1			T71	1		T68	21		T50	37
valid_sources[0x7e]	3423	1			T68	24		T50	23		T37	21
valid_sources[0x7f]	3616	1			T68	18		T50	37		T184	1
valid_sources[0x80]	3372	1			T73	1		T68	15		T50	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

319667

1

T28

1

T14

1

T42

2

values[0x0]

all_enables

biggest_size

138400

1

T6

1

T13

1

T28

1

values[0x1]

all_enables

biggest_size

138442

1

T6

1

T13

1

T14

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7911	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

102218

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30873	1			T68	709		T50	1327		T37	1022
values[0x0]	38633	1			T2	1		T6	1		T12	1
values[0x1]	40623	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5161	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

104968

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	457	1			T226	1		T76	2		T68	1
valid_sources[0x01]	266	1			T26	1		T68	2		T227	2
valid_sources[0x02]	681	1			T125	1		T128	1		T50	16
valid_sources[0x03]	463	1			T199	1		T228	1		T50	33
valid_sources[0x04]	348	1			T229	1		T26	1		T125	1
valid_sources[0x05]	289	1			T230	1		T231	1		T124	1
valid_sources[0x06]	472	1			T170	1		T232	1		T233	1
valid_sources[0x07]	562	1			T42	1		T234	1		T50	28
valid_sources[0x08]	277	1			T233	1		T50	20		T37	14
valid_sources[0x09]	625	1			T235	1		T236	4		T205	3
valid_sources[0x0a]	533	1			T65	1		T50	21		T181	6
valid_sources[0x0b]	263	1			T97	1		T50	19		T37	8
valid_sources[0x0c]	554	1			T68	13		T50	22		T37	21
valid_sources[0x0d]	613	1			T64	1		T237	16		T50	22
valid_sources[0x0e]	510	1			T238	1		T68	2		T50	13
valid_sources[0x0f]	292	1			T64	2		T68	2		T50	13
valid_sources[0x10]	359	1			T198	2		T50	22		T177	6
valid_sources[0x11]	399	1			T58	1		T77	8		T50	19
valid_sources[0x12]	701	1			T117	1		T239	1		T68	221
valid_sources[0x13]	309	1			T16	1		T118	1		T203	1
valid_sources[0x14]	553	1			T19	1		T235	1		T68	1
valid_sources[0x15]	259	1			T50	19		T37	12		T51	21
valid_sources[0x16]	385	1			T170	2		T240	1		T34	5
valid_sources[0x17]	741	1			T14	1		T143	1		T76	1
valid_sources[0x18]	425	1			T66	1		T92	3		T233	1
valid_sources[0x19]	362	1			T75	1		T241	1		T192	5
valid_sources[0x1a]	266	1			T118	1		T122	1		T50	17
valid_sources[0x1b]	294	1			T47	1		T223	1		T50	9
valid_sources[0x1c]	367	1			T45	1		T50	23		T37	14
valid_sources[0x1d]	483	1			T59	2		T238	1		T68	3
valid_sources[0x1e]	411	1			T238	1		T68	1		T50	15
valid_sources[0x1f]	406	1			T242	1		T219	1		T50	18
valid_sources[0x20]	328	1			T60	1		T47	1		T68	3
valid_sources[0x21]	206	1			T46	3		T238	1		T243	3
valid_sources[0x22]	502	1			T233	1		T50	19		T37	18
valid_sources[0x23]	406	1			T92	2		T59	2		T241	1
valid_sources[0x24]	672	1			T33	1		T236	1		T68	73
valid_sources[0x25]	261	1			T50	14		T37	10		T51	24
valid_sources[0x26]	615	1			T78	1		T195	5		T50	15
valid_sources[0x27]	306	1			T68	1		T244	1		T50	19
valid_sources[0x28]	536	1			T39	1		T243	1		T68	100
valid_sources[0x29]	438	1			T50	21		T37	8		T51	18
valid_sources[0x2a]	489	1			T231	1		T124	1		T50	17
valid_sources[0x2b]	725	1			T27	4		T68	108		T245	6
valid_sources[0x2c]	331	1			T119	1		T64	1		T50	21
valid_sources[0x2d]	340	1			T246	1		T35	1		T50	33
valid_sources[0x2e]	498	1			T247	3		T248	4		T68	2
valid_sources[0x2f]	432	1			T68	113		T249	1		T233	1
valid_sources[0x30]	357	1			T250	1		T251	1		T50	18
valid_sources[0x31]	407	1			T24	1		T52	1		T68	2
valid_sources[0x32]	414	1			T118	2		T231	1		T68	1
valid_sources[0x33]	498	1			T98	1		T170	1		T240	1
valid_sources[0x34]	413	1			T127	1		T252	1		T218	1
valid_sources[0x35]	403	1			T169	3		T171	4		T39	6
valid_sources[0x36]	552	1			T50	21		T37	21		T51	16
valid_sources[0x37]	394	1			T73	1		T253	8		T68	1
valid_sources[0x38]	562	1			T235	1		T224	2		T27	2
valid_sources[0x39]	367	1			T71	1		T199	1		T200	1
valid_sources[0x3a]	416	1			T68	79		T254	2		T50	23
valid_sources[0x3b]	750	1			T23	3		T255	1		T221	6
valid_sources[0x3c]	434	1			T50	23		T37	21		T51	12
valid_sources[0x3d]	424	1			T242	1		T227	2		T50	25
valid_sources[0x3e]	317	1			T68	1		T50	22		T37	13
valid_sources[0x3f]	485	1			T125	2		T50	21		T37	15
valid_sources[0x40]	466	1			T64	2		T231	1		T219	1
valid_sources[0x41]	440	1			T256	1		T80	1		T249	1
valid_sources[0x42]	394	1			T198	1		T236	4		T68	64
valid_sources[0x43]	357	1			T45	1		T186	1		T47	1
valid_sources[0x44]	340	1			T257	14		T249	1		T50	16
valid_sources[0x45]	462	1			T68	2		T228	1		T249	1
valid_sources[0x46]	266	1			T94	1		T258	2		T50	19
valid_sources[0x47]	236	1			T241	1		T240	1		T50	22
valid_sources[0x48]	408	1			T231	1		T50	23		T37	18
valid_sources[0x49]	469	1			T259	3		T50	18		T37	18
valid_sources[0x4a]	424	1			T117	1		T260	12		T50	18
valid_sources[0x4b]	463	1			T230	1		T50	12		T37	12
valid_sources[0x4c]	285	1			T2	1		T231	1		T50	20
valid_sources[0x4d]	363	1			T23	2		T50	22		T37	7
valid_sources[0x4e]	381	1			T261	1		T262	2		T263	1
valid_sources[0x4f]	417	1			T243	3		T50	20		T37	25
valid_sources[0x50]	277	1			T29	1		T25	1		T117	1
valid_sources[0x51]	375	1			T68	1		T9	2		T50	25
valid_sources[0x52]	340	1			T72	1		T50	20		T37	16
valid_sources[0x53]	436	1			T83	1		T118	1		T170	1
valid_sources[0x54]	490	1			T68	75		T264	1		T50	25
valid_sources[0x55]	484	1			T230	1		T259	2		T50	18
valid_sources[0x56]	445	1			T90	1		T265	1		T68	1
valid_sources[0x57]	709	1			T22	2		T247	1		T266	14
valid_sources[0x58]	554	1			T38	1		T20	1		T21	6
valid_sources[0x59]	282	1			T267	1		T50	17		T37	17
valid_sources[0x5a]	662	1			T50	16		T37	16		T51	9
valid_sources[0x5b]	557	1			T238	1		T50	20		T37	15
valid_sources[0x5c]	267	1			T245	1		T50	16		T220	2
valid_sources[0x5d]	369	1			T28	1		T22	2		T50	17
valid_sources[0x5e]	339	1			T238	2		T264	1		T50	22
valid_sources[0x5f]	668	1			T230	1		T238	1		T124	1
valid_sources[0x60]	528	1			T47	1		T268	2		T50	25
valid_sources[0x61]	373	1			T269	1		T17	1		T197	6
valid_sources[0x62]	276	1			T68	3		T245	3		T50	30
valid_sources[0x63]	308	1			T76	1		T79	9		T223	1
valid_sources[0x64]	512	1			T3	1		T46	1		T93	2
valid_sources[0x65]	783	1			T74	1		T172	19		T236	1
valid_sources[0x66]	373	1			T45	1		T270	2		T68	1
valid_sources[0x67]	417	1			T63	1		T68	2		T249	1
valid_sources[0x68]	206	1			T271	1		T50	21		T37	19
valid_sources[0x69]	493	1			T199	1		T223	1		T50	28
valid_sources[0x6a]	411	1			T69	1		T119	1		T50	13
valid_sources[0x6b]	694	1			T272	1		T64	1		T242	1
valid_sources[0x6c]	428	1			T194	1		T68	163		T249	1
valid_sources[0x6d]	334	1			T199	1		T76	1		T223	1
valid_sources[0x6e]	329	1			T13	1		T45	1		T247	2
valid_sources[0x6f]	369	1			T187	1		T68	18		T218	1
valid_sources[0x70]	302	1			T240	1		T203	5		T273	4
valid_sources[0x71]	242	1			T45	1		T242	1		T68	1
valid_sources[0x72]	517	1			T68	1		T244	1		T50	21
valid_sources[0x73]	563	1			T170	2		T50	11		T37	11
valid_sources[0x74]	674	1			T224	1		T50	26		T37	19
valid_sources[0x75]	335	1			T25	1		T241	1		T76	2
valid_sources[0x76]	473	1			T5	1		T68	3		T50	15
valid_sources[0x77]	362	1			T26	1		T76	2		T233	2
valid_sources[0x78]	553	1			T233	1		T50	12		T37	18
valid_sources[0x79]	339	1			T86	1		T68	1		T50	22
valid_sources[0x7a]	286	1			T274	1		T251	1		T50	23
valid_sources[0x7b]	339	1			T45	1		T50	13		T37	14
valid_sources[0x7c]	282	1			T57	1		T275	2		T68	1
valid_sources[0x7d]	524	1			T238	1		T258	3		T50	27
valid_sources[0x7e]	316	1			T251	1		T50	29		T37	14
valid_sources[0x7f]	581	1			T276	1		T230	1		T50	18
valid_sources[0x80]	299	1			T35	1		T50	23		T37	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26853

1

T68

649

T50

1241

T37

965

values[0x0]

all_enables

biggest_size

37662

1

T2

1

T6

1

T12

1

values[0x1]

all_enables

biggest_size

37703

1

T1

1

T3

1

T4

1