Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 705176 1 T3 1 T12 1 T13 1
full_word 611414 1 T6 2 T13 2 T28 2



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 1316320 1 T3 1 T6 2 T12 1
auto[TlIntgErrCmd] 96 1 T175 4 T188 2 T189 8
auto[TlIntgErrData] 97 1 T175 3 T188 6 T189 3
auto[TlIntgErrBoth] 77 1 T175 3 T188 2 T189 9



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 564695 1 T28 1 T14 1 T42 3
auto[1] 751895 1 T3 1 T6 2 T12 1



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 243078 1 T42 1 T69 7 T66 4
auto[TlIntgErrNone] partial auto[1] 461849 1 T3 1 T12 1 T13 1
auto[TlIntgErrNone] full_word auto[0] 321492 1 T28 1 T14 1 T42 2
auto[TlIntgErrNone] full_word auto[1] 289901 1 T6 2 T13 2 T28 1
auto[TlIntgErrCmd] partial auto[0] 46 1 T175 3 T188 2 T189 5
auto[TlIntgErrCmd] partial auto[1] 39 1 T189 1 T208 4 T210 2
auto[TlIntgErrCmd] full_word auto[0] 7 1 T175 1 T189 2 T215 2
auto[TlIntgErrCmd] full_word auto[1] 4 1 T216 1 T212 1 T217 1
auto[TlIntgErrData] partial auto[0] 39 1 T175 1 T188 4 T208 4
auto[TlIntgErrData] partial auto[1] 53 1 T175 1 T188 1 T189 2
auto[TlIntgErrData] full_word auto[0] 1 1 T189 1 - - - -
auto[TlIntgErrData] full_word auto[1] 4 1 T175 1 T188 1 T208 1
auto[TlIntgErrBoth] partial auto[0] 31 1 T175 3 T188 1 T189 3
auto[TlIntgErrBoth] partial auto[1] 41 1 T188 1 T189 3 T208 4
auto[TlIntgErrBoth] full_word auto[0] 1 1 T209 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 4 1 T189 3 T208 1 - -

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