Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T90

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90
1	1	Covered	T90

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T90
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	7990194	7988706	0	0
selKnown1	62478347	62476859	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	7990194	7988706	0	0
T1	7150	7148	0	0
T2	11136	11134	0	0
T3	1686	1684	0	0
T4	778	776	0	0
T5	2554	2552	0	0
T6	742	740	0	0
T7	4	2	0	0
T8	2	0	0	0
T12	1158	1156	0	0
T13	2660	2658	0	0
T14	2	0	0	0
T15	0	1	0	0
T19	2	0	0	0
T21	0	10	0	0
T24	4	2	0	0
T25	0	6	0	0
T28	1540	1538	0	0
T29	2	0	0	0
T30	0	12	0	0
T31	1804	1802	0	0
T42	2	0	0	0
T43	0	2	0	0
T44	0	9	0	0
T48	0	40	0	0
T69	2	0	0	0
T71	2	0	0	0
T82	0	1	0	0
T86	2	0	0	0
T90	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	62478347	62476859	0	0
T1	53807	53805	0	0
T2	32443	32441	0	0
T3	3138	3136	0	0
T4	2692	2690	0	0
T5	11772	11770	0	0
T6	3845	3843	0	0
T12	18116	18114	0	0
T13	41943	41941	0	0
T16	2	0	0	0
T21	0	10	0	0
T25	0	4	0	0
T28	31415	31413	0	0
T30	10	8	0	0
T31	29000	28998	0	0
T43	4	2	0	0
T44	10	8	0	0
T45	2	0	0	0
T48	42	40	0	0
T49	0	2	0	0
T53	0	2	0	0
T57	0	2	0	0
T94	2	0	0	0
T97	2	0	0	0
T98	2	0	0	0
T99	2	0	0	0
T117	0	4	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T90

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90
1	1	Covered	T90

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T90
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2579974	2579712	0	0
selKnown1	57068224	57067962	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2579974	2579712	0	0
T1	3575	3574	0	0
T2	5568	5567	0	0
T3	843	842	0	0
T4	389	388	0	0
T5	1277	1276	0	0
T6	371	370	0	0
T12	579	578	0	0
T13	1330	1329	0	0
T28	770	769	0	0
T31	902	901	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	57068224	57067962	0	0
T1	50232	50231	0	0
T2	26875	26874	0	0
T3	2295	2294	0	0
T4	2303	2302	0	0
T5	10495	10494	0	0
T6	3474	3473	0	0
T12	17537	17536	0	0
T13	40613	40612	0	0
T28	30645	30644	0	0
T31	28098	28097	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T90

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90
1	1	Covered	T90

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T90
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	751	489	0	0
selKnown1	711	449	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	751	489	0	0
T7	2	1	0	0
T8	1	0	0	0
T14	1	0	0	0
T19	1	0	0	0
T21	0	5	0	0
T24	2	1	0	0
T25	0	3	0	0
T29	1	0	0	0
T30	0	6	0	0
T42	1	0	0	0
T43	0	1	0	0
T44	0	4	0	0
T48	0	20	0	0
T69	1	0	0	0
T71	1	0	0	0
T82	0	1	0	0
T86	1	0	0	0
T186	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	711	449	0	0
T16	1	0	0	0
T21	0	5	0	0
T25	0	2	0	0
T30	5	4	0	0
T43	2	1	0	0
T44	5	4	0	0
T45	1	0	0	0
T48	21	20	0	0
T49	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T94	1	0	0	0
T97	1	0	0	0
T98	1	0	0	0
T99	1	0	0	0
T117	0	2	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T90

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90
1	1	Covered	T90

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T90
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	5407823	5407341	0	0
selKnown1	5407822	5407340	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407823	5407341	0	0
T1	3575	3574	0	0
T2	5568	5567	0	0
T3	843	842	0	0
T4	389	388	0	0
T5	1277	1276	0	0
T6	371	370	0	0
T12	579	578	0	0
T13	1330	1329	0	0
T28	770	769	0	0
T31	902	901	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	5407822	5407340	0	0
T1	3575	3574	0	0
T2	5568	5567	0	0
T3	843	842	0	0
T4	389	388	0	0
T5	1277	1276	0	0
T6	371	370	0	0
T12	579	578	0	0
T13	1330	1329	0	0
T28	770	769	0	0
T31	902	901	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T90

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90
1	1	Covered	T90

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T90
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1646	1164	0	0
selKnown1	1590	1108	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1646	1164	0	0
T7	2	1	0	0
T8	1	0	0	0
T14	1	0	0	0
T15	0	1	0	0
T19	1	0	0	0
T21	0	5	0	0
T24	2	1	0	0
T25	0	3	0	0
T29	1	0	0	0
T30	0	6	0	0
T42	1	0	0	0
T43	0	1	0	0
T44	0	5	0	0
T48	0	20	0	0
T69	1	0	0	0
T71	1	0	0	0
T86	1	0	0	0
T90	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1590	1108	0	0
T16	1	0	0	0
T21	0	5	0	0
T25	0	2	0	0
T30	5	4	0	0
T43	2	1	0	0
T44	5	4	0	0
T45	1	0	0	0
T48	21	20	0	0
T49	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T94	1	0	0	0
T97	1	0	0	0
T98	1	0	0	0
T99	1	0	0	0
T117	0	2	0	0