Toggle Coverage for Module :
prim_secded_inv_64_57_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T2,*T3,*T6 |
Yes |
T3,T6,T12 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T2,T3,T13 |
Yes |
T2,T3,T6 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T2,T3,T6 |
Yes |
T3,T6,T12 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T3,T6,T31 |
Yes |
T3,T6,T12 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T3,T6 |
Yes |
T3,T13,T31 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
158 |
60.77 |
Total Bits 0->1 |
130 |
79 |
60.77 |
Total Bits 1->0 |
130 |
79 |
60.77 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
158 |
60.77 |
Port Bits 0->1 |
130 |
79 |
60.77 |
Port Bits 1->0 |
130 |
79 |
60.77 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[5:0] |
Yes |
Yes |
*T2,*T24,*T20 |
Yes |
T20,T44,T21 |
INPUT |
data_i[56:6] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T2,T19,T20 |
Yes |
T2,T19,T29 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T2,T24,T20 |
Yes |
T20,T44,T21 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T20,T44,T21 |
Yes |
T12,T24,T20 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T20,T21,T85 |
Yes |
T24,T29,T20 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T3,*T6,*T31 |
Yes |
T3,T6,T31 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T3,T31,T7 |
Yes |
T6,T31,T7 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T3,T6,T31 |
Yes |
T3,T6,T31 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T3,T31,T7 |
Yes |
T3,T6,T42 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T3,T6,T31 |
Yes |
T3,T31,T7 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T6,*T13,*T14 |
Yes |
T3,T6,T12 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T13,T28,T42 |
Yes |
T3,T12,T13 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T6,T13,T14 |
Yes |
T3,T6,T12 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T6,T13,T42 |
Yes |
T6,T13,T42 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T3,T6 |
Yes |
T13,T14,T42 |
OUTPUT |
*Tests covering at least one bit in the range