Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts


Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 284870 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 636500 1 T2 1 T11 1 T12 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 537735 1 T12 1 T44 3 T56 80
values[0x0] 164125 1 T2 1 T11 2 T12 1
values[0x1] 219510 1 T3 1 T11 1 T12 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 190813 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 730557 1 T2 1 T3 1 T11 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3696 1 T66 1 T63 23 T9 15
valid_sources[0x01] 3989 1 T42 1 T63 13 T9 15
valid_sources[0x02] 2993 1 T66 1 T62 1 T204 1
valid_sources[0x03] 3894 1 T66 2 T63 12 T9 19
valid_sources[0x04] 3472 1 T63 17 T9 23 T26 51
valid_sources[0x05] 3718 1 T63 16 T9 11 T26 30
valid_sources[0x06] 3231 1 T12 1 T63 11 T9 24
valid_sources[0x07] 3286 1 T63 13 T9 8 T26 48
valid_sources[0x08] 4034 1 T63 18 T9 13 T26 36
valid_sources[0x09] 3545 1 T59 2 T63 11 T9 8
valid_sources[0x0a] 3741 1 T63 16 T9 16 T26 38
valid_sources[0x0b] 3673 1 T63 15 T9 15 T26 23
valid_sources[0x0c] 3492 1 T66 1 T63 23 T9 11
valid_sources[0x0d] 4327 1 T204 1 T63 16 T115 1
valid_sources[0x0e] 2911 1 T44 1 T63 20 T9 17
valid_sources[0x0f] 3437 1 T63 11 T9 19 T72 33
valid_sources[0x10] 3615 1 T66 3 T63 21 T9 9
valid_sources[0x11] 4445 1 T63 27 T9 30 T10 20
valid_sources[0x12] 3958 1 T63 21 T9 19 T72 22
valid_sources[0x13] 4533 1 T31 1 T63 18 T9 15
valid_sources[0x14] 3587 1 T63 17 T9 16 T26 45
valid_sources[0x15] 3536 1 T57 7 T218 1 T63 14
valid_sources[0x16] 3535 1 T63 11 T9 19 T26 27
valid_sources[0x17] 3467 1 T63 24 T9 10 T72 94
valid_sources[0x18] 3272 1 T63 13 T9 15 T26 34
valid_sources[0x19] 3696 1 T63 16 T9 13 T26 34
valid_sources[0x1a] 3514 1 T62 1 T63 16 T9 14
valid_sources[0x1b] 3744 1 T63 11 T9 18 T26 30
valid_sources[0x1c] 3308 1 T63 15 T9 11 T72 67
valid_sources[0x1d] 3574 1 T218 1 T63 16 T9 15
valid_sources[0x1e] 3210 1 T63 15 T9 10 T26 33
valid_sources[0x1f] 4114 1 T66 1 T59 1 T63 13
valid_sources[0x20] 3618 1 T63 16 T9 12 T26 48
valid_sources[0x21] 4120 1 T63 15 T9 18 T26 34
valid_sources[0x22] 3324 1 T63 20 T9 11 T72 6
valid_sources[0x23] 3397 1 T14 1 T63 11 T9 12
valid_sources[0x24] 3929 1 T63 10 T9 14 T26 34
valid_sources[0x25] 3223 1 T76 2 T63 22 T9 16
valid_sources[0x26] 3290 1 T63 8 T60 1 T9 13
valid_sources[0x27] 3795 1 T63 17 T9 14 T26 40
valid_sources[0x28] 3201 1 T63 14 T9 17 T202 1
valid_sources[0x29] 3634 1 T67 1 T63 16 T9 26
valid_sources[0x2a] 3612 1 T63 17 T116 2 T9 17
valid_sources[0x2b] 3611 1 T5 1 T63 9 T9 24
valid_sources[0x2c] 3658 1 T91 2 T63 10 T9 19
valid_sources[0x2d] 3988 1 T45 1 T66 2 T63 20
valid_sources[0x2e] 3273 1 T45 3 T63 15 T9 18
valid_sources[0x2f] 4472 1 T63 9 T9 8 T26 22
valid_sources[0x30] 3494 1 T66 2 T62 1 T63 10
valid_sources[0x31] 3535 1 T63 15 T9 17 T26 32
valid_sources[0x32] 3190 1 T56 2 T66 2 T63 13
valid_sources[0x33] 3683 1 T31 2 T63 14 T9 16
valid_sources[0x34] 3432 1 T63 7 T9 12 T72 10
valid_sources[0x35] 3634 1 T63 17 T9 12 T72 108
valid_sources[0x36] 3098 1 T63 14 T9 15 T26 27
valid_sources[0x37] 3879 1 T56 15 T66 1 T204 1
valid_sources[0x38] 3728 1 T63 17 T9 28 T26 17
valid_sources[0x39] 3499 1 T58 1 T63 14 T9 11
valid_sources[0x3a] 3576 1 T63 13 T60 1 T9 21
valid_sources[0x3b] 3812 1 T66 1 T63 23 T9 17
valid_sources[0x3c] 3731 1 T63 17 T60 2 T9 18
valid_sources[0x3d] 2976 1 T3 1 T66 1 T58 2
valid_sources[0x3e] 3968 1 T63 12 T9 16 T72 244
valid_sources[0x3f] 3450 1 T66 1 T63 14 T115 1
valid_sources[0x40] 3952 1 T66 3 T63 17 T9 13
valid_sources[0x41] 3416 1 T71 7 T63 18 T9 13
valid_sources[0x42] 3261 1 T62 1 T63 13 T115 1
valid_sources[0x43] 3307 1 T63 9 T9 13 T26 34
valid_sources[0x44] 3539 1 T63 19 T9 19 T72 4
valid_sources[0x45] 3509 1 T46 9 T63 15 T60 1
valid_sources[0x46] 4146 1 T41 2 T63 16 T9 7
valid_sources[0x47] 3497 1 T63 17 T9 14 T26 31
valid_sources[0x48] 4231 1 T63 20 T9 15 T194 2
valid_sources[0x49] 3063 1 T63 8 T9 16 T26 32
valid_sources[0x4a] 3454 1 T56 6 T63 13 T9 7
valid_sources[0x4b] 3740 1 T63 22 T9 13 T26 24
valid_sources[0x4c] 3345 1 T93 1 T63 14 T9 24
valid_sources[0x4d] 3560 1 T66 5 T63 9 T9 11
valid_sources[0x4e] 3419 1 T63 12 T9 19 T26 33
valid_sources[0x4f] 3110 1 T62 1 T59 1 T85 1
valid_sources[0x50] 3236 1 T63 12 T8 1 T9 22
valid_sources[0x51] 3857 1 T63 14 T9 8 T26 38
valid_sources[0x52] 3581 1 T63 9 T9 9 T72 134
valid_sources[0x53] 3984 1 T63 20 T182 1 T9 14
valid_sources[0x54] 4216 1 T63 7 T9 27 T26 31
valid_sources[0x55] 3488 1 T63 14 T9 15 T26 44
valid_sources[0x56] 3499 1 T63 18 T9 16 T72 1
valid_sources[0x57] 3327 1 T63 16 T8 4 T9 10
valid_sources[0x58] 3494 1 T66 3 T63 13 T9 18
valid_sources[0x59] 4078 1 T75 2 T63 10 T9 12
valid_sources[0x5a] 3064 1 T63 13 T9 22 T26 47
valid_sources[0x5b] 3555 1 T32 4 T181 2 T63 13
valid_sources[0x5c] 3915 1 T11 1 T63 15 T9 18
valid_sources[0x5d] 3505 1 T45 1 T63 9 T9 16
valid_sources[0x5e] 2807 1 T63 15 T9 14 T26 34
valid_sources[0x5f] 3531 1 T63 9 T9 22 T26 42
valid_sources[0x60] 5161 1 T25 3 T63 22 T9 13
valid_sources[0x61] 3418 1 T63 15 T9 14 T72 114
valid_sources[0x62] 3239 1 T66 2 T218 1 T63 23
valid_sources[0x63] 3080 1 T63 21 T9 9 T26 23
valid_sources[0x64] 3465 1 T63 12 T9 9 T26 23
valid_sources[0x65] 3441 1 T63 15 T9 14 T26 39
valid_sources[0x66] 3034 1 T54 1 T66 1 T63 15
valid_sources[0x67] 3179 1 T2 1 T44 1 T63 11
valid_sources[0x68] 3972 1 T63 11 T9 6 T26 25
valid_sources[0x69] 4070 1 T63 10 T9 14 T26 29
valid_sources[0x6a] 4166 1 T62 1 T67 1 T63 13
valid_sources[0x6b] 3604 1 T58 2 T63 9 T9 30
valid_sources[0x6c] 3583 1 T63 17 T9 14 T26 26
valid_sources[0x6d] 3500 1 T44 1 T63 11 T9 12
valid_sources[0x6e] 3643 1 T66 1 T63 20 T9 13
valid_sources[0x6f] 3506 1 T63 19 T9 16 T26 30
valid_sources[0x70] 3356 1 T63 19 T9 19 T72 135
valid_sources[0x71] 2997 1 T58 1 T63 10 T9 22
valid_sources[0x72] 3845 1 T63 19 T9 20 T26 41
valid_sources[0x73] 3937 1 T58 1 T63 17 T9 20
valid_sources[0x74] 3435 1 T63 19 T9 11 T26 26
valid_sources[0x75] 3628 1 T63 16 T9 14 T72 94
valid_sources[0x76] 3602 1 T63 9 T9 10 T26 26
valid_sources[0x77] 2919 1 T63 17 T9 14 T26 37
valid_sources[0x78] 3153 1 T63 17 T9 12 T72 135
valid_sources[0x79] 2968 1 T56 4 T66 3 T63 27
valid_sources[0x7a] 4065 1 T67 2 T63 13 T9 15
valid_sources[0x7b] 3297 1 T63 8 T9 29 T72 44
valid_sources[0x7c] 3520 1 T62 1 T63 16 T9 16
valid_sources[0x7d] 3420 1 T63 15 T9 6 T26 28
valid_sources[0x7e] 3176 1 T56 5 T218 1 T63 11
valid_sources[0x7f] 4089 1 T56 2 T63 12 T9 16
valid_sources[0x80] 3276 1 T58 6 T63 17 T9 16



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 322982 1 T44 2 T56 80 T45 9
values[0x0] all_enables biggest_size 156808 1 T2 1 T11 1 T12 1
values[0x1] all_enables biggest_size 156710 1 T5 1 T44 2 T14 1


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 8621 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 107091 1 T1 1 T2 1 T3 1



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 33366 1 T63 757 T9 475 T72 280
values[0x0] 40166 1 T2 1 T18 1 T5 1
values[0x1] 42180 1 T1 1 T3 1 T11 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5748 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 109964 1 T1 1 T2 1 T3 1



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 425 1 T72 2 T26 35 T73 45
valid_sources[0x01] 559 1 T110 5 T72 5 T26 28
valid_sources[0x02] 425 1 T63 46 T121 1 T110 1
valid_sources[0x03] 471 1 T164 6 T63 1 T9 2
valid_sources[0x04] 419 1 T18 1 T63 42 T72 4
valid_sources[0x05] 450 1 T64 1 T63 15 T72 10
valid_sources[0x06] 340 1 T69 1 T72 7 T26 22
valid_sources[0x07] 338 1 T90 1 T63 2 T219 2
valid_sources[0x08] 593 1 T80 1 T220 1 T72 2
valid_sources[0x09] 523 1 T63 31 T72 3 T26 24
valid_sources[0x0a] 517 1 T40 1 T72 7 T26 26
valid_sources[0x0b] 394 1 T25 1 T63 1 T221 1
valid_sources[0x0c] 335 1 T72 3 T26 38 T83 16
valid_sources[0x0d] 375 1 T63 1 T72 10 T26 17
valid_sources[0x0e] 536 1 T63 48 T72 3 T26 17
valid_sources[0x0f] 357 1 T219 1 T72 2 T26 26
valid_sources[0x10] 423 1 T63 1 T72 1 T26 23
valid_sources[0x11] 417 1 T63 41 T21 2 T72 4
valid_sources[0x12] 453 1 T14 1 T72 1 T26 25
valid_sources[0x13] 386 1 T106 1 T63 2 T72 3
valid_sources[0x14] 548 1 T109 2 T63 36 T72 14
valid_sources[0x15] 341 1 T72 2 T26 9 T73 43
valid_sources[0x16] 561 1 T29 1 T63 1 T72 3
valid_sources[0x17] 449 1 T63 7 T72 4 T26 18
valid_sources[0x18] 330 1 T63 5 T220 1 T72 10
valid_sources[0x19] 397 1 T63 2 T72 3 T26 12
valid_sources[0x1a] 452 1 T181 1 T63 1 T72 11
valid_sources[0x1b] 381 1 T63 24 T26 15 T73 8
valid_sources[0x1c] 431 1 T63 2 T72 10 T26 19
valid_sources[0x1d] 453 1 T63 18 T9 37 T72 1
valid_sources[0x1e] 486 1 T72 6 T26 26 T73 13
valid_sources[0x1f] 474 1 T72 2 T26 20 T73 74
valid_sources[0x20] 461 1 T85 1 T184 1 T63 13
valid_sources[0x21] 560 1 T63 21 T72 8 T26 18
valid_sources[0x22] 416 1 T72 3 T26 17 T199 1
valid_sources[0x23] 343 1 T81 1 T111 1 T60 1
valid_sources[0x24] 392 1 T77 1 T63 10 T9 4
valid_sources[0x25] 794 1 T72 11 T26 26 T73 32
valid_sources[0x26] 387 1 T63 23 T72 1 T26 24
valid_sources[0x27] 454 1 T97 2 T63 1 T117 1
valid_sources[0x28] 389 1 T63 20 T69 1 T72 1
valid_sources[0x29] 511 1 T63 39 T72 2 T26 17
valid_sources[0x2a] 784 1 T72 8 T26 18 T73 90
valid_sources[0x2b] 388 1 T9 1 T221 1 T72 2
valid_sources[0x2c] 411 1 T19 2 T9 3 T72 1
valid_sources[0x2d] 455 1 T46 1 T72 11 T26 13
valid_sources[0x2e] 430 1 T196 1 T63 2 T72 5
valid_sources[0x2f] 381 1 T63 3 T21 1 T72 3
valid_sources[0x30] 427 1 T6 1 T48 2 T66 1
valid_sources[0x31] 522 1 T63 7 T72 2 T26 19
valid_sources[0x32] 387 1 T63 4 T72 23 T26 15
valid_sources[0x33] 969 1 T3 1 T7 1 T63 3
valid_sources[0x34] 602 1 T109 2 T63 24 T72 4
valid_sources[0x35] 395 1 T72 4 T222 1 T26 20
valid_sources[0x36] 402 1 T84 1 T72 3 T26 32
valid_sources[0x37] 712 1 T63 52 T72 5 T26 24
valid_sources[0x38] 327 1 T63 1 T72 3 T26 22
valid_sources[0x39] 329 1 T223 1 T63 2 T72 6
valid_sources[0x3a] 371 1 T162 4 T63 1 T72 7
valid_sources[0x3b] 523 1 T63 3 T220 1 T72 5
valid_sources[0x3c] 377 1 T162 2 T63 14 T72 8
valid_sources[0x3d] 525 1 T63 15 T72 9 T26 21
valid_sources[0x3e] 859 1 T63 16 T72 4 T26 16
valid_sources[0x3f] 650 1 T63 49 T72 5 T26 26
valid_sources[0x40] 412 1 T162 1 T63 23 T72 4
valid_sources[0x41] 360 1 T224 1 T63 3 T72 3
valid_sources[0x42] 434 1 T63 17 T220 1 T72 3
valid_sources[0x43] 506 1 T63 9 T72 1 T26 17
valid_sources[0x44] 435 1 T90 1 T63 6 T225 1
valid_sources[0x45] 391 1 T9 53 T26 19 T73 30
valid_sources[0x46] 362 1 T72 4 T26 21 T73 5
valid_sources[0x47] 354 1 T63 3 T116 1 T72 6
valid_sources[0x48] 349 1 T72 4 T26 32 T73 25
valid_sources[0x49] 373 1 T63 45 T72 7 T26 25
valid_sources[0x4a] 377 1 T112 1 T63 3 T226 1
valid_sources[0x4b] 345 1 T48 1 T63 16 T21 2
valid_sources[0x4c] 274 1 T63 1 T72 1 T26 22
valid_sources[0x4d] 625 1 T2 1 T60 2 T227 1
valid_sources[0x4e] 477 1 T63 21 T26 26 T73 50
valid_sources[0x4f] 409 1 T228 1 T63 14 T26 21
valid_sources[0x50] 320 1 T72 3 T26 30 T73 42
valid_sources[0x51] 453 1 T63 10 T72 8 T26 16
valid_sources[0x52] 448 1 T63 2 T229 1 T220 1
valid_sources[0x53] 752 1 T9 1 T72 6 T26 29
valid_sources[0x54] 384 1 T63 15 T9 39 T26 32
valid_sources[0x55] 389 1 T45 1 T63 10 T230 9
valid_sources[0x56] 513 1 T24 1 T63 17 T9 114
valid_sources[0x57] 412 1 T63 12 T72 1 T26 16
valid_sources[0x58] 357 1 T39 1 T63 43 T9 6
valid_sources[0x59] 416 1 T132 1 T63 30 T219 1
valid_sources[0x5a] 610 1 T63 1 T72 3 T26 26
valid_sources[0x5b] 421 1 T63 33 T201 1 T72 5
valid_sources[0x5c] 403 1 T63 1 T72 6 T26 22
valid_sources[0x5d] 378 1 T63 8 T9 1 T72 2
valid_sources[0x5e] 407 1 T90 1 T120 1 T9 31
valid_sources[0x5f] 333 1 T63 1 T72 2 T26 18
valid_sources[0x60] 347 1 T63 2 T72 4 T26 25
valid_sources[0x61] 382 1 T63 1 T72 2 T231 1
valid_sources[0x62] 318 1 T219 1 T72 2 T26 19
valid_sources[0x63] 319 1 T63 36 T231 1 T26 31
valid_sources[0x64] 554 1 T72 3 T26 23 T73 4
valid_sources[0x65] 327 1 T231 1 T26 16 T73 53
valid_sources[0x66] 608 1 T232 1 T63 19 T72 5
valid_sources[0x67] 322 1 T233 1 T72 9 T26 20
valid_sources[0x68] 329 1 T63 4 T26 19 T73 35
valid_sources[0x69] 594 1 T86 1 T63 1 T194 1
valid_sources[0x6a] 454 1 T59 1 T63 4 T72 8
valid_sources[0x6b] 655 1 T63 30 T72 13 T26 39
valid_sources[0x6c] 557 1 T60 1 T72 2 T26 20
valid_sources[0x6d] 341 1 T63 1 T72 1 T26 28
valid_sources[0x6e] 453 1 T76 1 T63 33 T72 8
valid_sources[0x6f] 520 1 T4 1 T72 5 T26 19
valid_sources[0x70] 614 1 T63 15 T72 2 T26 17
valid_sources[0x71] 458 1 T63 21 T9 65 T219 1
valid_sources[0x72] 463 1 T9 84 T233 1 T72 7
valid_sources[0x73] 318 1 T40 1 T72 4 T26 17
valid_sources[0x74] 438 1 T63 3 T9 5 T72 9
valid_sources[0x75] 323 1 T231 1 T26 19 T73 44
valid_sources[0x76] 324 1 T72 1 T26 16 T73 36
valid_sources[0x77] 370 1 T43 1 T72 14 T26 33
valid_sources[0x78] 379 1 T178 1 T63 67 T72 3
valid_sources[0x79] 385 1 T63 3 T72 2 T26 27
valid_sources[0x7a] 402 1 T56 1 T63 9 T72 5
valid_sources[0x7b] 595 1 T58 2 T63 55 T72 3
valid_sources[0x7c] 428 1 T53 2 T107 2 T63 28
valid_sources[0x7d] 633 1 T115 1 T233 1 T72 2
valid_sources[0x7e] 671 1 T9 189 T72 1 T26 37
valid_sources[0x7f] 348 1 T31 6 T63 10 T72 3
valid_sources[0x80] 354 1 T90 1 T63 4 T119 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 28893 1 T63 722 T9 441 T72 264
values[0x0] all_enables biggest_size 39165 1 T2 1 T18 1 T5 1
values[0x1] all_enables biggest_size 39033 1 T1 1 T3 1 T11 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%