Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

710937

1

T3

1

T11

2

T12

2

full_word

650539

1

T2

1

T11

1

T12

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1361176	1			T2	1		T3	1		T11	3
auto[TlIntgErrCmd]	108	1			T165	5		T179	1		T180	6
auto[TlIntgErrData]	105	1			T165	3		T179	4		T180	5
auto[TlIntgErrBoth]	87	1			T165	2		T179	5		T180	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

555550

1

T12

1

T44

3

T56

80

auto[1]

805926

1

T2

1

T3

1

T11

3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	230897	1			T12	1		T44	1		T14	1
auto[TlIntgErrNone]	partial	auto[1]	479766	1			T3	1		T11	2		T12	1
auto[TlIntgErrNone]	full_word	auto[0]	324516	1			T44	2		T56	80		T45	9
auto[TlIntgErrNone]	full_word	auto[1]	325997	1			T2	1		T11	1		T12	1
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T165	2		T180	3		T166	1
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T165	3		T179	1		T180	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T208	1		T214	1		T215	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T180	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T165	1		T179	2		T180	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T165	2		T179	1		T180	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T208	1		T211	1		T216	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T179	1		T210	2		T217	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T179	4		T180	6		T207	1
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T165	2		T179	1		T180	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T208	1		T217	1		T214	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T207	1		T208	1		T214	1