Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 90.48 97.60 100.00 93.75 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 101682802 131442 0 0
late_debug_enable_rd_A 101682802 9993 0 0
late_debug_enable_regwen_rd_A 101682802 9274 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101682802 131442 0 0
T8 246754 0 0 0
T9 0 2857 0 0
T26 0 8151 0 0
T27 0 7679 0 0
T60 336877 0 0 0
T61 0 6644 0 0
T63 149699 3534 0 0
T72 0 1382 0 0
T73 0 9756 0 0
T74 0 4938 0 0
T83 0 4365 0 0
T103 0 7104 0 0
T115 9647 0 0 0
T116 16800 0 0 0
T117 140209 0 0 0
T118 107561 0 0 0
T119 2185 0 0 0
T120 269495 0 0 0
T121 139340 0 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101682802 9993 0 0
T27 379917 1597 0 0
T74 0 1706 0 0
T126 0 5 0 0
T129 0 210 0 0
T130 0 7 0 0
T140 0 3 0 0
T142 0 263 0 0
T143 0 8 0 0
T165 0 31 0 0
T166 0 39 0 0
T167 46241 0 0 0
T168 830121 0 0 0
T169 2228 0 0 0
T170 205054 0 0 0
T171 184446 0 0 0
T172 2913 0 0 0
T173 327257 0 0 0
T174 1538 0 0 0
T175 217152 0 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 101682802 9274 0 0
T27 379917 1335 0 0
T74 0 1692 0 0
T126 0 7 0 0
T129 0 214 0 0
T130 0 1 0 0
T142 0 218 0 0
T143 0 12 0 0
T165 0 29 0 0
T166 0 60 0 0
T167 46241 0 0 0
T168 830121 0 0 0
T169 2228 0 0 0
T170 205054 0 0 0
T171 184446 0 0 0
T172 2913 0 0 0
T173 327257 0 0 0
T174 1538 0 0 0
T175 217152 0 0 0
T176 0 157 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%