Line Coverage for Module :
tlul_cmd_intg_gen
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 20 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 46 | 4 | 4 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
19 tl_h2d_cmd_intg_t cmd;
20 1/1 assign cmd = extract_h2d_cmd_intg(tl_i);
Tests: T1 T2 T3
21 logic [H2DCmdMaxWidth-1:0] unused_cmd_payload;
22
23 logic [H2DCmdIntgWidth-1:0] cmd_intg;
24 prim_secded_inv_64_57_enc u_cmd_gen (
25 .data_i(H2DCmdMaxWidth'(cmd)),
26 .data_o({cmd_intg, unused_cmd_payload})
27 );
28
29 logic [top_pkg::TL_DW-1:0] data_final;
30 logic [DataIntgWidth-1:0] data_intg;
31
32 if (EnableDataIntgGen) begin : gen_data_intg
33 1/1 assign data_final = tl_i.a_data;
Tests: T1 T2 T3
34
35 logic [DataMaxWidth-1:0] unused_data;
36 prim_secded_inv_39_32_enc u_data_gen (
37 .data_i(DataMaxWidth'(data_final)),
38 .data_o({data_intg, unused_data})
39 );
40 end else begin : gen_passthrough_data_intg
41 assign data_final = tl_i.a_data;
42 assign data_intg = tl_i.a_user.data_intg;
43 end
44
45 always_comb begin
46 1/1 tl_o = tl_i;
Tests: T1 T2 T3
47 1/1 tl_o.a_data = data_final;
Tests: T1 T2 T3
48 1/1 tl_o.a_user.cmd_intg = cmd_intg;
Tests: T1 T2 T3
49 1/1 tl_o.a_user.data_intg = data_intg;
Tests: T1 T2 T3
50 end
51
52
53 logic unused_tl;
54 1/1 assign unused_tl = ^tl_i;
Tests: T1 T2 T3
Assert Coverage for Module :
tlul_cmd_intg_gen
Assertion Details
PayMaxWidthCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483 |
483 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |