Module Definition
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Module : rv_dm_enable_checker
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.enable_checker 100.00 100.00 100.00



Module Instance : tb.dut.enable_checker

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 90.48 97.60 100.00 93.75 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm_enable_checker
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3611100.00

28 logic late_debug_enable; 29 1/1 assign late_debug_enable = Tests: T1 T2 T3  30 mubi8_test_true_strict(otp_dis_rv_dm_late_debug_i) || 31 mubi32_test_true_strict(prim_mubi_pkg::mubi32_t'(regs_reg2hw.late_debug_enable)); 32 33 // Should debug be enabled? If we're using late_debug_enable, this is governed by 34 // lc_hw_debug_en_i. If not, it comes from lc_dft_en_i. 35 logic debug_enabled; 36 1/1 assign debug_enabled = lc_tx_test_true_strict(late_debug_enable ? lc_hw_debug_en_i : lc_dft_en_i); Tests: T2 T5 T44 

Assert Coverage for Module : rv_dm_enable_checker
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugRequestNeedsDebug_A 50620713 50553168 0 0
MemTLResponseWithoutDebugIsError_A 50509092 50441547 0 0
NdmResetAckNeedsDebug_A 50621515 50553970 0 0
SbaTLRequestNeedsDebug_A 50509092 50441547 0 0


DebugRequestNeedsDebug_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50620713 50553168 0 0
T1 11240 11189 0 0
T2 8108 8028 0 0
T3 21327 21253 0 0
T4 2321 2257 0 0
T5 2102 2032 0 0
T11 10141 10057 0 0
T12 7467 7409 0 0
T13 42032 41955 0 0
T18 47212 47161 0 0
T44 29676 29615 0 0

MemTLResponseWithoutDebugIsError_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50509092 50441547 0 0
T1 11240 11189 0 0
T2 8108 8028 0 0
T3 21327 21253 0 0
T4 2321 2257 0 0
T5 2102 2032 0 0
T11 10141 10057 0 0
T12 7467 7409 0 0
T13 42032 41955 0 0
T18 47212 47161 0 0
T44 29676 29615 0 0

NdmResetAckNeedsDebug_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50621515 50553970 0 0
T1 11240 11189 0 0
T2 8108 8028 0 0
T3 21327 21253 0 0
T4 2321 2257 0 0
T5 2102 2032 0 0
T11 10141 10057 0 0
T12 7467 7409 0 0
T13 42032 41955 0 0
T18 47212 47161 0 0
T44 29676 29615 0 0

SbaTLRequestNeedsDebug_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 50509092 50441547 0 0
T1 11240 11189 0 0
T2 8108 8028 0 0
T3 21327 21253 0 0
T4 2321 2257 0 0
T5 2102 2032 0 0
T11 10141 10057 0 0
T12 7467 7409 0 0
T13 42032 41955 0 0
T18 47212 47161 0 0
T44 29676 29615 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%