Unified Coverage Report :: Module :: prim_secded_inv_39_32_dec

Module : prim_secded_inv_39_32_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk	100.00			100.00
tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk	100.00			100.00
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk	100.00			100.00

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						gen_rsp_data_intg_check.u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_tlul_data_integ_dec

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_39_32_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T2,T12,T18	Yes	T1,T2,T3	INPUT
data_o[31:0]	Yes	Yes	T2,T12,T18	Yes	T1,T2,T3	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T12,T5	Yes	T12,T18,T5	OUTPUT
err_o[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T24,T28,T49	Yes	T1,T3,T24	INPUT
data_o[31:0]	Yes	Yes	T24,T28,T49	Yes	T1,T3,T24	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T24,T88	Yes	T45,T88,T49	OUTPUT
err_o[1:0]	Yes	Yes	T1,T3,T24	Yes	T1,T3,T24	OUTPUT

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T2,T12,T18	Yes	T18,T19,T20	INPUT
data_o[31:0]	Yes	Yes	T2,T12,T18	Yes	T18,T19,T20	OUTPUT
syndrome_o[6:0]	Yes	Yes	T19,T41,T86	Yes	T12,T4,T44	OUTPUT
err_o[1:0]	Yes	Yes	T19,T86,T87	Yes	T4,T44,T19	OUTPUT

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	160	160	100.00
Total Bits 0->1	80	80	100.00
Total Bits 1->0	80	80	100.00

Ports	4	4	100.00
Port Bits	160	160	100.00
Port Bits 0->1	80	80	100.00
Port Bits 1->0	80	80	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[38:0]	Yes	Yes	T5,T44,T19	Yes	T2,T12,T18	INPUT
data_o[31:0]	Yes	Yes	T5,T44,T19	Yes	T2,T12,T18	OUTPUT
syndrome_o[6:0]	Yes	Yes	T12,T5,T25	Yes	T12,T18,T5	OUTPUT
err_o[1:0]	Yes	Yes	T2,T3,T11	Yes	T2,T12,T5	OUTPUT