Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT80

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT80
11CoveredT80

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT80
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7535508 7534016 0 0
selKnown1 55737774 55736282 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7535508 7534016 0 0
T1 7782 7780 0 0
T2 1916 1914 0 0
T3 1048 1046 0 0
T4 686 684 0 0
T5 728 726 0 0
T6 3 1 0 0
T7 4 2 0 0
T11 2846 2844 0 0
T12 1540 1538 0 0
T13 1786 1784 0 0
T14 2 0 0 0
T18 9486 9484 0 0
T19 4 2 0 0
T20 2 0 0 0
T24 2 0 0 0
T40 0 3 0 0
T44 2504 2502 0 0
T45 2 0 0 0
T47 0 2 0 0
T48 0 9 0 0
T52 0 20 0 0
T56 2 0 0 0
T77 0 2 0 0
T79 0 1 0 0
T80 3 1 0 0
T88 2 0 0 0
T177 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 55737774 55736282 0 0
T1 15131 15129 0 0
T2 9066 9064 0 0
T3 21851 21849 0 0
T4 2664 2662 0 0
T5 2466 2464 0 0
T6 2 0 0 0
T7 2 0 0 0
T11 11564 11562 0 0
T12 8237 8235 0 0
T13 42925 42923 0 0
T14 2 0 0 0
T18 51955 51953 0 0
T19 4 2 0 0
T20 2 0 0 0
T24 2 0 0 0
T40 0 2 0 0
T44 30928 30926 0 0
T45 2 0 0 0
T47 0 2 0 0
T48 0 8 0 0
T52 0 40 0 0
T53 0 2 0 0
T56 2 0 0 0
T80 2 0 0 0
T84 0 2 0 0
T87 0 20 0 0
T88 2 0 0 0
T89 0 20 0 0
T109 0 8 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT80

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT80
11CoveredT80

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT80
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2419146 2418883 0 0
selKnown1 50621515 50621252 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2419146 2418883 0 0
T1 3891 3890 0 0
T2 958 957 0 0
T3 524 523 0 0
T4 343 342 0 0
T5 364 363 0 0
T11 1423 1422 0 0
T12 770 769 0 0
T13 893 892 0 0
T18 4743 4742 0 0
T44 1252 1251 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 50621515 50621252 0 0
T1 11240 11239 0 0
T2 8108 8107 0 0
T3 21327 21326 0 0
T4 2321 2320 0 0
T5 2102 2101 0 0
T11 10141 10140 0 0
T12 7467 7466 0 0
T13 42032 42031 0 0
T18 47212 47211 0 0
T44 29676 29675 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT80

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT80
11CoveredT80

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT80
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 813 550 0 0
selKnown1 762 499 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 813 550 0 0
T6 1 0 0 0
T7 2 1 0 0
T14 1 0 0 0
T19 2 1 0 0
T20 1 0 0 0
T24 1 0 0 0
T40 0 1 0 0
T45 1 0 0 0
T47 0 1 0 0
T48 0 4 0 0
T52 0 20 0 0
T53 0 1 0 0
T56 1 0 0 0
T77 0 1 0 0
T78 0 1 0 0
T80 1 0 0 0
T88 1 0 0 0
T177 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 762 499 0 0
T6 1 0 0 0
T7 1 0 0 0
T14 1 0 0 0
T19 2 1 0 0
T20 1 0 0 0
T24 1 0 0 0
T40 0 1 0 0
T45 1 0 0 0
T47 0 1 0 0
T48 0 4 0 0
T52 0 20 0 0
T53 0 1 0 0
T56 1 0 0 0
T80 1 0 0 0
T84 0 1 0 0
T87 0 10 0 0
T88 1 0 0 0
T89 0 10 0 0
T109 0 4 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT80

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT80
11CoveredT80

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT80
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 5113782 5113299 0 0
selKnown1 5113781 5113298 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 5113782 5113299 0 0
T1 3891 3890 0 0
T2 958 957 0 0
T3 524 523 0 0
T4 343 342 0 0
T5 364 363 0 0
T11 1423 1422 0 0
T12 770 769 0 0
T13 893 892 0 0
T18 4743 4742 0 0
T44 1252 1251 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 5113781 5113298 0 0
T1 3891 3890 0 0
T2 958 957 0 0
T3 524 523 0 0
T4 343 342 0 0
T5 364 363 0 0
T11 1423 1422 0 0
T12 770 769 0 0
T13 893 892 0 0
T18 4743 4742 0 0
T44 1252 1251 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00

16 // We model the mux with logic operations for GTECH runs. 17 1/1 assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT80

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT80
11CoveredT80

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT80
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1767 1284 0 0
selKnown1 1716 1233 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1767 1284 0 0
T6 2 1 0 0
T7 2 1 0 0
T14 1 0 0 0
T19 2 1 0 0
T20 1 0 0 0
T24 1 0 0 0
T40 0 2 0 0
T45 1 0 0 0
T47 0 1 0 0
T48 0 5 0 0
T56 1 0 0 0
T77 0 1 0 0
T79 0 1 0 0
T80 2 1 0 0
T88 1 0 0 0
T177 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1716 1233 0 0
T6 1 0 0 0
T7 1 0 0 0
T14 1 0 0 0
T19 2 1 0 0
T20 1 0 0 0
T24 1 0 0 0
T40 0 1 0 0
T45 1 0 0 0
T47 0 1 0 0
T48 0 4 0 0
T52 0 20 0 0
T53 0 1 0 0
T56 1 0 0 0
T80 1 0 0 0
T84 0 1 0 0
T87 0 10 0 0
T88 1 0 0 0
T89 0 10 0 0
T109 0 4 0 0

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