Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 5/5 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Line Coverage for Module :
prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 unreachable if (!rst_ni) begin
85 unreachable unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unreachable unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 1/1 assign lc_en = lc_en_i;
Tests: T1 T2 T3
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 2/2 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3
Assert Coverage for Module :
prim_lc_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1578 |
1578 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T11 |
6 |
6 |
0 |
0 |
T12 |
6 |
6 |
0 |
0 |
T13 |
6 |
6 |
0 |
0 |
T18 |
6 |
6 |
0 |
0 |
T44 |
6 |
6 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
303616667 |
303211397 |
0 |
0 |
T1 |
67440 |
67134 |
0 |
0 |
T2 |
48648 |
48168 |
0 |
0 |
T3 |
127962 |
127518 |
0 |
0 |
T4 |
13926 |
13542 |
0 |
0 |
T5 |
12612 |
12192 |
0 |
0 |
T11 |
60846 |
60342 |
0 |
0 |
T12 |
44802 |
44454 |
0 |
0 |
T13 |
252192 |
251730 |
0 |
0 |
T18 |
283272 |
282966 |
0 |
0 |
T44 |
178056 |
177690 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151864545 |
151655052 |
0 |
2367 |
T1 |
33720 |
33558 |
0 |
9 |
T2 |
24324 |
24075 |
0 |
9 |
T3 |
63981 |
63750 |
0 |
9 |
T4 |
6963 |
6762 |
0 |
9 |
T5 |
6306 |
6087 |
0 |
9 |
T11 |
30423 |
30162 |
0 |
9 |
T12 |
22401 |
22218 |
0 |
9 |
T13 |
126096 |
125856 |
0 |
9 |
T18 |
141636 |
141474 |
0 |
9 |
T44 |
89028 |
88836 |
0 |
9 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151752122 |
151549487 |
0 |
0 |
T1 |
33720 |
33567 |
0 |
0 |
T2 |
24324 |
24084 |
0 |
0 |
T3 |
63981 |
63759 |
0 |
0 |
T4 |
6963 |
6771 |
0 |
0 |
T5 |
6306 |
6096 |
0 |
0 |
T11 |
30423 |
30171 |
0 |
0 |
T12 |
22401 |
22227 |
0 |
0 |
T13 |
126096 |
125865 |
0 |
0 |
T18 |
141636 |
141483 |
0 |
0 |
T44 |
89028 |
88845 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
263 |
263 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50621515 |
50553970 |
0 |
0 |
T1 |
11240 |
11189 |
0 |
0 |
T2 |
8108 |
8028 |
0 |
0 |
T3 |
21327 |
21253 |
0 |
0 |
T4 |
2321 |
2257 |
0 |
0 |
T5 |
2102 |
2032 |
0 |
0 |
T11 |
10141 |
10057 |
0 |
0 |
T12 |
7467 |
7409 |
0 |
0 |
T13 |
42032 |
41955 |
0 |
0 |
T18 |
47212 |
47161 |
0 |
0 |
T44 |
29676 |
29615 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50621515 |
50551684 |
0 |
789 |
T1 |
11240 |
11186 |
0 |
3 |
T2 |
8108 |
8025 |
0 |
3 |
T3 |
21327 |
21250 |
0 |
3 |
T4 |
2321 |
2254 |
0 |
3 |
T5 |
2102 |
2029 |
0 |
3 |
T11 |
10141 |
10054 |
0 |
3 |
T12 |
7467 |
7406 |
0 |
3 |
T13 |
42032 |
41952 |
0 |
3 |
T18 |
47212 |
47158 |
0 |
3 |
T44 |
29676 |
29612 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 1/1 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3
Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
263 |
263 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50621515 |
50553970 |
0 |
0 |
T1 |
11240 |
11189 |
0 |
0 |
T2 |
8108 |
8028 |
0 |
0 |
T3 |
21327 |
21253 |
0 |
0 |
T4 |
2321 |
2257 |
0 |
0 |
T5 |
2102 |
2032 |
0 |
0 |
T11 |
10141 |
10057 |
0 |
0 |
T12 |
7467 |
7409 |
0 |
0 |
T13 |
42032 |
41955 |
0 |
0 |
T18 |
47212 |
47161 |
0 |
0 |
T44 |
29676 |
29615 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50621515 |
50551684 |
0 |
789 |
T1 |
11240 |
11186 |
0 |
3 |
T2 |
8108 |
8025 |
0 |
3 |
T3 |
21327 |
21250 |
0 |
3 |
T4 |
2321 |
2254 |
0 |
3 |
T5 |
2102 |
2029 |
0 |
3 |
T11 |
10141 |
10054 |
0 |
3 |
T12 |
7467 |
7406 |
0 |
3 |
T13 |
42032 |
41952 |
0 |
3 |
T18 |
47212 |
47158 |
0 |
3 |
T44 |
29676 |
29612 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_pm_en_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i) begin
68 1/1 lc_en_in_sva_q <= lc_en_i;
Tests: T1 T2 T3
69 end
70 `ASSERT(OutputDelay_A,
71 rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73 `endif
74 end else begin : gen_no_flops
75 //VCS coverage off
76 // pragma coverage off
77
78 // This unused companion logic helps remove lint errors
79 // for modules where clock and reset are used for assertions only
80 // or nothing at all.
81 // This logic will be removed for sythesis since it is unloaded.
82 lc_ctrl_pkg::lc_tx_t unused_logic;
83 always_ff @(posedge clk_i or negedge rst_ni) begin
84 if (!rst_ni) begin
85 unused_logic <= lc_ctrl_pkg::Off;
86 end else begin
87 unused_logic <= lc_en_i;
88 end
89 end
90 //VCS coverage on
91 // pragma coverage on
92
93 assign lc_en = lc_en_i;
94
95 `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96 end
97
98 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101 prim_sec_anchor_buf u_prim_buf (
102 .in_i(lc_en[k]),
103 .out_o(lc_en_out[k])
104 );
105 end
106 3/3 assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Assert Coverage for Instance : tb.dut.u_pm_en_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
263 |
263 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T44 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50621515 |
50553970 |
0 |
0 |
T1 |
11240 |
11189 |
0 |
0 |
T2 |
8108 |
8028 |
0 |
0 |
T3 |
21327 |
21253 |
0 |
0 |
T4 |
2321 |
2257 |
0 |
0 |
T5 |
2102 |
2032 |
0 |
0 |
T11 |
10141 |
10057 |
0 |
0 |
T12 |
7467 |
7409 |
0 |
0 |
T13 |
42032 |
41955 |
0 |
0 |
T18 |
47212 |
47161 |
0 |
0 |
T44 |
29676 |
29615 |
0 |
0 |
gen_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50621515 |
50551684 |
0 |
789 |
T1 |
11240 |
11186 |
0 |
3 |
T2 |
8108 |
8025 |
0 |
3 |
T3 |
21327 |
21250 |
0 |
3 |
T4 |
2321 |
2254 |
0 |
3 |
T5 |
2102 |
2029 |
0 |
3 |
T11 |
10141 |
10054 |
0 |
3 |
T12 |
7467 |
7406 |
0 |
3 |
T13 |
42032 |
41952 |
0 |
3 |
T18 |
47212 |
47158 |
0 |
3 |
T44 |
29676 |
29612 |
0 |
3 |