SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_mubi32_sync_late_debug_enable | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.36 | 100.00 | 90.48 | 97.60 | 100.00 | 93.75 | dut |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
144 always_ff @(posedge clk_i or negedge rst_ni) begin 145 unreachable if (!rst_ni) begin 146 unreachable unused_logic <= MuBi32False; 147 end else begin 148 unreachable unused_logic <= mubi_i; 149 end 150 end 151 152 //VCS coverage on 153 // pragma coverage on 154 155 1/1 assign mubi = MuBi32Width'(mubi_i); Tests: T1 T2 T3 156 157 `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) 158 end 159 160 for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs 161 logic [MuBi32Width-1:0] mubi_out; 162 for (genvar k = 0; k < MuBi32Width; k++) begin : gen_bits 163 prim_buf u_prim_buf ( 164 .in_i(mubi[k]), 165 .out_o(mubi_out[k]) 166 ); 167 end 168 4/4 assign mubi_o[j] = mubi32_t'(mubi_out); Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3 | T1 T2 T3
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 263 | 263 | 0 | 0 |
OutputsKnown_A | 50621515 | 50553970 | 0 | 0 |
gen_no_flops.OutputDelay_A | 50621515 | 50553970 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 263 | 263 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T44 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50621515 | 50553970 | 0 | 0 |
T1 | 11240 | 11189 | 0 | 0 |
T2 | 8108 | 8028 | 0 | 0 |
T3 | 21327 | 21253 | 0 | 0 |
T4 | 2321 | 2257 | 0 | 0 |
T5 | 2102 | 2032 | 0 | 0 |
T11 | 10141 | 10057 | 0 | 0 |
T12 | 7467 | 7409 | 0 | 0 |
T13 | 42032 | 41955 | 0 | 0 |
T18 | 47212 | 47161 | 0 | 0 |
T44 | 29676 | 29615 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 50621515 | 50553970 | 0 | 0 |
T1 | 11240 | 11189 | 0 | 0 |
T2 | 8108 | 8028 | 0 | 0 |
T3 | 21327 | 21253 | 0 | 0 |
T4 | 2321 | 2257 | 0 | 0 |
T5 | 2102 | 2032 | 0 | 0 |
T11 | 10141 | 10057 | 0 | 0 |
T12 | 7467 | 7409 | 0 | 0 |
T13 | 42032 | 41955 | 0 | 0 |
T18 | 47212 | 47161 | 0 | 0 |
T44 | 29676 | 29615 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |