Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	322369	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

731700

1

T7

2

T44

3

T31

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	598429	1			T5	1		T44	3		T57	80
values[0x0]	197172	1			T3	1		T5	1		T13	1
values[0x1]	258468	1			T2	1		T5	1		T13	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	218318	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

835751

1

T5

1

T7

2

T44

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4235	1			T66	2		T191	1		T12	19
valid_sources[0x01]	3647	1			T63	3		T66	2		T60	1
valid_sources[0x02]	3859	1			T12	14		T82	17		T83	40
valid_sources[0x03]	4063	1			T11	2		T12	19		T39	71
valid_sources[0x04]	4230	1			T15	1		T12	23		T205	1
valid_sources[0x05]	4188	1			T169	1		T27	2		T12	24
valid_sources[0x06]	5976	1			T12	15		T82	34		T83	33
valid_sources[0x07]	4099	1			T12	22		T82	24		T83	30
valid_sources[0x08]	4565	1			T12	17		T70	461		T69	2
valid_sources[0x09]	4006	1			T12	19		T39	3		T205	1
valid_sources[0x0a]	3537	1			T12	27		T69	1		T82	33
valid_sources[0x0b]	4070	1			T12	10		T82	22		T83	26
valid_sources[0x0c]	4290	1			T18	6		T12	18		T70	37
valid_sources[0x0d]	3769	1			T37	1		T27	1		T12	25
valid_sources[0x0e]	4308	1			T12	18		T39	59		T40	2
valid_sources[0x0f]	4225	1			T12	24		T82	20		T83	25
valid_sources[0x10]	3596	1			T12	14		T70	2		T82	20
valid_sources[0x11]	4007	1			T54	1		T12	24		T82	24
valid_sources[0x12]	4575	1			T17	8		T11	1		T12	14
valid_sources[0x13]	3654	1			T191	1		T12	16		T82	23
valid_sources[0x14]	3790	1			T12	26		T69	2		T82	23
valid_sources[0x15]	3601	1			T60	1		T12	8		T39	39
valid_sources[0x16]	4005	1			T74	1		T12	24		T70	114
valid_sources[0x17]	4823	1			T66	1		T12	18		T39	6
valid_sources[0x18]	4106	1			T12	11		T69	1		T82	18
valid_sources[0x19]	4571	1			T169	1		T12	16		T82	23
valid_sources[0x1a]	4292	1			T37	1		T206	1		T12	13
valid_sources[0x1b]	3703	1			T12	17		T19	1		T82	19
valid_sources[0x1c]	3796	1			T94	1		T116	1		T12	14
valid_sources[0x1d]	3744	1			T12	5		T82	25		T83	45
valid_sources[0x1e]	5544	1			T66	1		T12	18		T70	37
valid_sources[0x1f]	4333	1			T11	1		T12	22		T82	20
valid_sources[0x20]	4826	1			T207	1		T12	18		T39	20
valid_sources[0x21]	3802	1			T206	1		T12	26		T19	1
valid_sources[0x22]	3706	1			T12	16		T82	30		T83	39
valid_sources[0x23]	3927	1			T12	12		T82	23		T83	30
valid_sources[0x24]	3790	1			T12	22		T208	2		T82	24
valid_sources[0x25]	3781	1			T54	1		T191	1		T12	24
valid_sources[0x26]	3770	1			T32	1		T187	2		T12	16
valid_sources[0x27]	4078	1			T12	20		T209	3		T82	24
valid_sources[0x28]	4205	1			T12	26		T189	1		T82	23
valid_sources[0x29]	3914	1			T5	3		T11	1		T12	22
valid_sources[0x2a]	3744	1			T66	1		T12	25		T70	45
valid_sources[0x2b]	3863	1			T12	17		T69	1		T82	29
valid_sources[0x2c]	3960	1			T2	1		T31	3		T12	22
valid_sources[0x2d]	4656	1			T12	20		T70	56		T82	22
valid_sources[0x2e]	3535	1			T12	14		T210	3		T82	26
valid_sources[0x2f]	3769	1			T206	1		T12	18		T82	21
valid_sources[0x30]	4058	1			T12	22		T82	33		T83	25
valid_sources[0x31]	5779	1			T12	16		T70	90		T211	5
valid_sources[0x32]	4908	1			T12	14		T35	1		T82	14
valid_sources[0x33]	4180	1			T12	21		T35	1		T82	30
valid_sources[0x34]	3408	1			T10	3		T37	1		T12	17
valid_sources[0x35]	3730	1			T12	14		T82	26		T83	23
valid_sources[0x36]	3810	1			T192	1		T11	1		T12	19
valid_sources[0x37]	3637	1			T66	1		T12	19		T19	1
valid_sources[0x38]	3927	1			T12	22		T212	2		T82	37
valid_sources[0x39]	3780	1			T192	1		T12	10		T70	125
valid_sources[0x3a]	4078	1			T12	17		T70	382		T39	25
valid_sources[0x3b]	3915	1			T45	1		T37	3		T12	14
valid_sources[0x3c]	4384	1			T36	7		T11	1		T12	18
valid_sources[0x3d]	3709	1			T66	2		T12	14		T82	28
valid_sources[0x3e]	3708	1			T12	14		T39	9		T82	24
valid_sources[0x3f]	3580	1			T66	1		T11	1		T12	25
valid_sources[0x40]	3797	1			T30	3		T12	19		T39	38
valid_sources[0x41]	4189	1			T12	15		T35	1		T82	19
valid_sources[0x42]	4580	1			T64	1		T12	15		T19	1
valid_sources[0x43]	3977	1			T192	1		T12	16		T70	135
valid_sources[0x44]	3638	1			T12	9		T82	29		T83	38
valid_sources[0x45]	3778	1			T33	1		T12	17		T82	30
valid_sources[0x46]	3433	1			T12	18		T39	62		T82	26
valid_sources[0x47]	4378	1			T66	2		T12	10		T82	20
valid_sources[0x48]	4970	1			T12	16		T19	2		T82	27
valid_sources[0x49]	4447	1			T61	1		T12	14		T39	7
valid_sources[0x4a]	3882	1			T12	21		T70	8		T205	1
valid_sources[0x4b]	4178	1			T12	17		T70	14		T82	19
valid_sources[0x4c]	4097	1			T12	14		T35	1		T82	22
valid_sources[0x4d]	3641	1			T12	22		T70	47		T213	1
valid_sources[0x4e]	4011	1			T12	19		T70	68		T82	13
valid_sources[0x4f]	3527	1			T12	13		T39	16		T82	21
valid_sources[0x50]	4801	1			T12	16		T82	28		T214	11
valid_sources[0x51]	3951	1			T12	18		T70	3		T39	67
valid_sources[0x52]	13024	1			T12	34		T82	38		T215	2
valid_sources[0x53]	3825	1			T12	13		T39	40		T82	27
valid_sources[0x54]	4647	1			T12	17		T39	6		T82	22
valid_sources[0x55]	4040	1			T64	6		T12	17		T39	43
valid_sources[0x56]	3918	1			T12	17		T70	56		T82	29
valid_sources[0x57]	3741	1			T45	1		T12	19		T82	26
valid_sources[0x58]	5116	1			T12	15		T70	9		T39	297
valid_sources[0x59]	4477	1			T45	1		T60	1		T12	20
valid_sources[0x5a]	3831	1			T37	1		T12	13		T70	82
valid_sources[0x5b]	3905	1			T12	17		T39	12		T82	27
valid_sources[0x5c]	4617	1			T66	4		T192	3		T96	1
valid_sources[0x5d]	3623	1			T12	21		T39	135		T209	3
valid_sources[0x5e]	4164	1			T7	1		T66	3		T37	1
valid_sources[0x5f]	3660	1			T66	1		T12	22		T39	16
valid_sources[0x60]	3660	1			T12	19		T69	1		T205	1
valid_sources[0x61]	4089	1			T12	13		T39	58		T82	39
valid_sources[0x62]	3718	1			T12	17		T216	1		T82	24
valid_sources[0x63]	3841	1			T12	21		T70	49		T82	24
valid_sources[0x64]	4277	1			T12	14		T82	29		T83	36
valid_sources[0x65]	4340	1			T12	13		T19	2		T39	29
valid_sources[0x66]	4272	1			T37	1		T12	18		T70	28
valid_sources[0x67]	3876	1			T12	13		T70	16		T69	1
valid_sources[0x68]	3907	1			T12	18		T39	125		T82	20
valid_sources[0x69]	3781	1			T13	1		T60	1		T37	1
valid_sources[0x6a]	9092	1			T37	2		T12	22		T39	170
valid_sources[0x6b]	5337	1			T12	14		T70	19		T69	1
valid_sources[0x6c]	4043	1			T62	9		T12	18		T70	29
valid_sources[0x6d]	3914	1			T66	3		T10	5		T12	20
valid_sources[0x6e]	3905	1			T26	2		T207	1		T12	20
valid_sources[0x6f]	3605	1			T12	31		T70	31		T82	23
valid_sources[0x70]	3972	1			T66	3		T12	21		T39	66
valid_sources[0x71]	4095	1			T11	1		T12	9		T70	174
valid_sources[0x72]	3640	1			T37	1		T12	20		T82	23
valid_sources[0x73]	4051	1			T12	16		T70	52		T35	1
valid_sources[0x74]	4372	1			T45	1		T66	2		T12	19
valid_sources[0x75]	4878	1			T12	17		T39	17		T209	1
valid_sources[0x76]	3994	1			T13	1		T41	1		T12	19
valid_sources[0x77]	4670	1			T12	20		T70	21		T38	2
valid_sources[0x78]	4447	1			T66	3		T59	1		T12	24
valid_sources[0x79]	4262	1			T12	21		T82	27		T83	44
valid_sources[0x7a]	3746	1			T66	1		T12	8		T39	30
valid_sources[0x7b]	4128	1			T37	1		T12	13		T82	20
valid_sources[0x7c]	3698	1			T191	1		T12	25		T39	3
valid_sources[0x7d]	4035	1			T61	1		T12	21		T82	32
valid_sources[0x7e]	4205	1			T12	14		T70	97		T216	1
valid_sources[0x7f]	4112	1			T12	16		T39	20		T68	1
valid_sources[0x80]	4104	1			T34	14		T12	16		T217	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

353474

1

T44

2

T57

80

T63

7

values[0x0]

all_enables

biggest_size

188861

1

T7

1

T44

1

T31

1

values[0x1]

all_enables

biggest_size

189365

1

T7

1

T168

1

T64

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9534	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

114506

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35218	1			T12	774		T70	709		T39	759
values[0x0]	43083	1			T1	1		T2	1		T3	1
values[0x1]	45739	1			T5	1		T14	1		T21	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6267	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

117773

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	395	1			T8	1		T70	7		T39	8
valid_sources[0x01]	382	1			T39	6		T211	2		T83	29
valid_sources[0x02]	474	1			T31	1		T54	1		T70	1
valid_sources[0x03]	433	1			T125	1		T70	10		T39	12
valid_sources[0x04]	519	1			T70	9		T39	14		T218	1
valid_sources[0x05]	441	1			T39	12		T219	3		T216	1
valid_sources[0x06]	390	1			T119	1		T39	14		T83	29
valid_sources[0x07]	531	1			T39	13		T82	104		T83	40
valid_sources[0x08]	492	1			T39	16		T220	3		T82	1
valid_sources[0x09]	427	1			T12	1		T39	19		T221	1
valid_sources[0x0a]	402	1			T222	1		T39	15		T194	1
valid_sources[0x0b]	449	1			T39	13		T82	33		T83	29
valid_sources[0x0c]	377	1			T171	5		T70	4		T39	11
valid_sources[0x0d]	528	1			T39	13		T223	2		T83	28
valid_sources[0x0e]	363	1			T39	8		T220	2		T82	1
valid_sources[0x0f]	641	1			T224	2		T225	1		T19	1
valid_sources[0x10]	530	1			T17	1		T11	3		T39	9
valid_sources[0x11]	465	1			T3	1		T70	1		T39	13
valid_sources[0x12]	419	1			T19	1		T39	11		T226	21
valid_sources[0x13]	665	1			T70	1		T39	12		T82	1
valid_sources[0x14]	457	1			T22	1		T227	1		T69	1
valid_sources[0x15]	490	1			T39	14		T82	1		T228	1
valid_sources[0x16]	460	1			T27	1		T39	11		T35	1
valid_sources[0x17]	484	1			T12	8		T39	13		T229	1
valid_sources[0x18]	355	1			T46	1		T70	1		T39	8
valid_sources[0x19]	511	1			T84	2		T70	3		T39	9
valid_sources[0x1a]	532	1			T70	1		T177	1		T39	8
valid_sources[0x1b]	355	1			T12	4		T39	5		T229	1
valid_sources[0x1c]	472	1			T230	1		T39	7		T231	1
valid_sources[0x1d]	454	1			T70	1		T39	8		T216	1
valid_sources[0x1e]	437	1			T171	1		T39	9		T83	22
valid_sources[0x1f]	520	1			T37	1		T39	6		T232	1
valid_sources[0x20]	387	1			T180	2		T39	15		T83	20
valid_sources[0x21]	570	1			T13	1		T17	1		T233	1
valid_sources[0x22]	543	1			T37	1		T19	1		T39	10
valid_sources[0x23]	533	1			T18	2		T12	41		T39	12
valid_sources[0x24]	415	1			T39	11		T234	7		T83	30
valid_sources[0x25]	620	1			T95	2		T70	159		T39	9
valid_sources[0x26]	379	1			T65	1		T224	1		T39	20
valid_sources[0x27]	642	1			T123	4		T70	49		T39	9
valid_sources[0x28]	388	1			T235	4		T39	8		T236	1
valid_sources[0x29]	429	1			T96	1		T39	10		T38	3
valid_sources[0x2a]	469	1			T224	2		T39	7		T237	6
valid_sources[0x2b]	382	1			T87	1		T238	1		T39	13
valid_sources[0x2c]	468	1			T6	1		T222	1		T39	10
valid_sources[0x2d]	412	1			T70	37		T39	15		T83	29
valid_sources[0x2e]	417	1			T230	1		T39	7		T83	22
valid_sources[0x2f]	649	1			T22	1		T225	2		T12	133
valid_sources[0x30]	391	1			T12	1		T70	3		T180	3
valid_sources[0x31]	529	1			T118	7		T190	3		T70	1
valid_sources[0x32]	630	1			T66	1		T230	1		T39	12
valid_sources[0x33]	638	1			T62	1		T22	1		T239	1
valid_sources[0x34]	533	1			T39	8		T205	2		T240	1
valid_sources[0x35]	428	1			T70	1		T39	8		T241	1
valid_sources[0x36]	390	1			T75	1		T178	1		T39	17
valid_sources[0x37]	445	1			T18	1		T39	14		T82	1
valid_sources[0x38]	421	1			T27	1		T39	8		T189	1
valid_sources[0x39]	438	1			T225	2		T39	7		T242	5
valid_sources[0x3a]	427	1			T39	13		T82	1		T243	1
valid_sources[0x3b]	376	1			T39	7		T189	1		T244	7
valid_sources[0x3c]	361	1			T245	2		T246	1		T39	10
valid_sources[0x3d]	468	1			T33	1		T19	1		T39	11
valid_sources[0x3e]	412	1			T247	1		T39	12		T82	3
valid_sources[0x3f]	730	1			T70	65		T39	5		T82	2
valid_sources[0x40]	513	1			T248	1		T69	1		T39	9
valid_sources[0x41]	483	1			T22	1		T39	6		T83	18
valid_sources[0x42]	630	1			T43	1		T70	123		T39	9
valid_sources[0x43]	386	1			T96	1		T70	1		T69	1
valid_sources[0x44]	502	1			T70	114		T39	12		T249	1
valid_sources[0x45]	430	1			T49	1		T64	1		T89	1
valid_sources[0x46]	374	1			T41	1		T88	1		T99	1
valid_sources[0x47]	426	1			T23	1		T222	1		T39	11
valid_sources[0x48]	440	1			T56	1		T96	2		T39	12
valid_sources[0x49]	426	1			T172	4		T27	2		T39	7
valid_sources[0x4a]	414	1			T172	2		T239	1		T23	3
valid_sources[0x4b]	338	1			T37	2		T39	11		T219	4
valid_sources[0x4c]	425	1			T70	3		T39	16		T229	1
valid_sources[0x4d]	390	1			T39	12		T249	1		T82	1
valid_sources[0x4e]	417	1			T190	1		T70	1		T177	1
valid_sources[0x4f]	534	1			T70	112		T39	16		T220	1
valid_sources[0x50]	642	1			T70	218		T39	17		T194	1
valid_sources[0x51]	677	1			T12	175		T70	1		T39	13
valid_sources[0x52]	563	1			T12	140		T179	1		T39	19
valid_sources[0x53]	391	1			T33	1		T39	14		T250	1
valid_sources[0x54]	436	1			T86	1		T33	1		T172	1
valid_sources[0x55]	426	1			T12	9		T70	4		T39	10
valid_sources[0x56]	482	1			T195	1		T95	1		T12	70
valid_sources[0x57]	415	1			T27	1		T39	11		T251	1
valid_sources[0x58]	472	1			T91	1		T119	1		T12	1
valid_sources[0x59]	567	1			T225	1		T70	111		T39	20
valid_sources[0x5a]	743	1			T7	1		T70	108		T39	13
valid_sources[0x5b]	354	1			T233	1		T252	1		T39	12
valid_sources[0x5c]	949	1			T48	4		T59	1		T18	1
valid_sources[0x5d]	419	1			T235	1		T39	9		T249	1
valid_sources[0x5e]	751	1			T70	162		T39	12		T82	1
valid_sources[0x5f]	475	1			T170	2		T253	1		T245	2
valid_sources[0x60]	470	1			T245	1		T224	1		T27	1
valid_sources[0x61]	421	1			T70	1		T39	8		T220	2
valid_sources[0x62]	410	1			T39	8		T221	1		T254	1
valid_sources[0x63]	537	1			T225	1		T12	92		T128	1
valid_sources[0x64]	446	1			T22	1		T126	7		T39	11
valid_sources[0x65]	486	1			T120	1		T70	2		T39	13
valid_sources[0x66]	983	1			T70	40		T39	5		T82	155
valid_sources[0x67]	590	1			T70	1		T39	17		T255	1
valid_sources[0x68]	483	1			T100	1		T70	3		T39	10
valid_sources[0x69]	491	1			T233	1		T70	115		T39	11
valid_sources[0x6a]	576	1			T37	1		T39	10		T256	1
valid_sources[0x6b]	567	1			T12	120		T177	1		T39	15
valid_sources[0x6c]	453	1			T11	2		T39	14		T83	22
valid_sources[0x6d]	431	1			T52	1		T39	7		T257	1
valid_sources[0x6e]	396	1			T117	2		T70	1		T246	1
valid_sources[0x6f]	442	1			T183	1		T39	17		T258	3
valid_sources[0x70]	400	1			T70	2		T39	5		T216	1
valid_sources[0x71]	606	1			T39	15		T216	1		T82	20
valid_sources[0x72]	416	1			T32	1		T125	1		T70	4
valid_sources[0x73]	419	1			T85	1		T70	1		T39	12
valid_sources[0x74]	566	1			T80	1		T12	86		T125	2
valid_sources[0x75]	398	1			T70	3		T39	10		T219	1
valid_sources[0x76]	847	1			T70	1		T39	10		T35	1
valid_sources[0x77]	411	1			T39	8		T83	22		T71	23
valid_sources[0x78]	442	1			T39	8		T82	10		T83	32
valid_sources[0x79]	519	1			T39	9		T189	1		T241	1
valid_sources[0x7a]	501	1			T55	1		T259	1		T39	10
valid_sources[0x7b]	594	1			T39	13		T40	1		T82	103
valid_sources[0x7c]	368	1			T170	1		T74	1		T222	1
valid_sources[0x7d]	379	1			T260	1		T19	1		T70	1
valid_sources[0x7e]	544	1			T39	13		T261	6		T83	19
valid_sources[0x7f]	389	1			T121	1		T39	11		T83	25
valid_sources[0x80]	479	1			T70	2		T39	6		T83	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30433

1

T12

739

T70

666

T39

728

values[0x0]

all_enables

biggest_size

41921

1

T1

1

T2

1

T3

1

values[0x1]

all_enables

biggest_size

42152

1

T5

1

T14

1

T21

1