Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

802131

1

T2

1

T3

1

T5

3

full_word

748423

1

T7

2

T44

3

T31

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1550194	1			T2	1		T3	1		T5	3
auto[TlIntgErrCmd]	133	1			T185	9		T174	10		T176	7
auto[TlIntgErrData]	115	1			T185	6		T174	5		T176	11
auto[TlIntgErrBoth]	112	1			T185	5		T174	5		T176	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619688

1

T5

1

T44

3

T57

80

auto[1]

930866

1

T2

1

T3

1

T5

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	264088	1			T5	1		T44	1		T15	1
auto[TlIntgErrNone]	partial	auto[1]	537715	1			T2	1		T3	1		T5	2
auto[TlIntgErrNone]	full_word	auto[0]	355445	1			T44	2		T57	80		T63	7
auto[TlIntgErrNone]	full_word	auto[1]	392946	1			T7	2		T44	1		T31	1
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T185	4		T174	3		T176	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T185	4		T174	6		T176	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T176	1		T197	1		T200	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T185	1		T174	1		T176	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T185	3		T174	2		T176	6
auto[TlIntgErrData]	partial	auto[1]	60	1			T185	2		T174	3		T176	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T185	1		T199	1		T203	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T176	1		T199	1		T201	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T185	1		T176	1		T199	3
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T185	4		T174	2		T176	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T174	1		T199	2		T200	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T174	2		T198	1		T204	1