Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	102801730	150934	0	0
late_debug_enable_rd_A	102801730	11667	0	0
late_debug_enable_regwen_rd_A	102801730	10763	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102801730	150934	0	0
T12	174401	3233	0	0
T19	333667	0	0	0
T39	0	3233	0	0
T58	0	16251	0	0
T70	194621	3497	0	0
T71	0	11172	0	0
T73	0	15121	0	0
T82	0	4499	0	0
T83	0	8457	0	0
T110	0	18583	0	0
T111	0	5355	0	0
T123	3631	0	0	0
T124	163887	0	0	0
T125	62125	0	0	0
T126	4659	0	0	0
T127	321727	0	0	0
T128	34972	0	0	0
T129	516894	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102801730	11667	0	0
T39	0	1232	0	0
T70	194621	1187	0	0
T82	0	1353	0	0
T127	321727	0	0	0
T128	34972	0	0	0
T129	516894	0	0	0
T134	0	4	0	0
T148	0	3	0	0
T162	0	12	0	0
T173	0	133	0	0
T174	0	80	0	0
T175	0	93	0	0
T176	0	34	0	0
T177	4444	0	0	0
T178	19554	0	0	0
T179	111527	0	0	0
T180	1723	0	0	0
T181	111426	0	0	0
T182	200105	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102801730	10763	0	0
T39	0	1035	0	0
T70	194621	1015	0	0
T82	0	1204	0	0
T127	321727	0	0	0
T128	34972	0	0	0
T129	516894	0	0	0
T134	0	2	0	0
T148	0	3	0	0
T162	0	41	0	0
T173	0	100	0	0
T174	0	82	0	0
T175	0	71	0	0
T176	0	85	0	0
T177	4444	0	0	0
T178	19554	0	0	0
T179	111527	0	0	0
T180	1723	0	0	0
T181	111426	0	0	0
T182	200105	0	0	0