Module Definition
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Module : prim_secded_inv_39_32_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_dec.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk 100.00 100.00
tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk 100.00 100.00
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk 100.00 100.00


Module Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 gen_rsp_data_intg_check.u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_39_32_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T2,T3,T5 Yes T2,T3,T4 OUTPUT
err_o[1:0] Yes Yes T1,T3,T31 Yes T4,T5,T44 OUTPUT

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[38:0] Yes Yes T3,T31,T25 Yes T3,T5,T25 INPUT
data_o[31:0] Yes Yes T3,T31,T25 Yes T3,T5,T25 OUTPUT
syndrome_o[6:0] Yes Yes T3,T5,T25 Yes T3,T5,T31 OUTPUT
err_o[1:0] Yes Yes T3,T31,T25 Yes T5,T15,T9 OUTPUT

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.gen_rsp_data_intg_check.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[38:0] Yes Yes T1,T8,T31 Yes T1,T43,T85 INPUT
data_o[31:0] Yes Yes T1,T8,T31 Yes T1,T43,T85 OUTPUT
syndrome_o[6:0] Yes Yes T46,T88,T90 Yes T2,T44,T25 OUTPUT
err_o[1:0] Yes Yes T88,T90,T36 Yes T4,T44,T8 OUTPUT

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[38:0] Yes Yes T2,T44,T57 Yes T1,T2,T4 INPUT
data_o[31:0] Yes Yes T2,T44,T57 Yes T1,T2,T4 OUTPUT
syndrome_o[6:0] Yes Yes T2,T48,T92 Yes T2,T4,T32 OUTPUT
err_o[1:0] Yes Yes T1,T2,T3 Yes T15,T42,T32 OUTPUT