Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T79

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T79
1	1	Covered	T79

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T79
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8370201	8368709	0	0
selKnown1	65611790	65610298	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	8370201	8368709	0	0
T1	12774	12772	0	0
T2	1158	1156	0	0
T3	1868	1866	0	0
T4	646	644	0	0
T5	1498	1496	0	0
T6	7574	7572	0	0
T7	762	760	0	0
T8	4	2	0	0
T9	3	1	0	0
T13	1802	1800	0	0
T14	4060	4058	0	0
T15	2	0	0	0
T25	2	0	0	0
T31	2	0	0	0
T43	2	0	0	0
T44	2702	2700	0	0
T46	4	2	0	0
T47	0	40	0	0
T48	0	9	0	0
T52	0	1	0	0
T57	2	0	0	0
T63	2	0	0	0
T75	0	2	0	0
T78	0	1	0	0
T79	3	1	0	0
T88	0	2	0	0
T183	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	65611790	65610298	0	0
T1	46196	46194	0	0
T2	5600	5598	0	0
T3	20841	20839	0	0
T4	8031	8029	0	0
T5	39499	39497	0	0
T6	71710	71708	0	0
T7	17048	17046	0	0
T13	30132	30130	0	0
T14	35640	35638	0	0
T16	2	0	0	0
T29	2	0	0	0
T30	2	0	0	0
T42	2	0	0	0
T44	15996	15994	0	0
T45	2	0	0	0
T46	4	2	0	0
T47	0	40	0	0
T48	0	8	0	0
T49	2	0	0	0
T52	0	2	0	0
T75	2	0	0	0
T84	0	2	0	0
T86	0	2	0	0
T88	0	2	0	0
T90	0	20	0	0
T91	2	0	0	0
T92	0	20	0	0
T100	2	0	0	0
T117	0	2	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T79

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T79
1	1	Covered	T79

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T79
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2710774	2710511	0	0
selKnown1	59952497	59952234	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2710774	2710511	0	0
T1	6387	6386	0	0
T2	579	578	0	0
T3	934	933	0	0
T4	323	322	0	0
T5	749	748	0	0
T6	3787	3786	0	0
T7	381	380	0	0
T13	901	900	0	0
T14	2030	2029	0	0
T44	1351	1350	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	59952497	59952234	0	0
T1	39809	39808	0	0
T2	5021	5020	0	0
T3	19907	19906	0	0
T4	7708	7707	0	0
T5	38750	38749	0	0
T6	67923	67922	0	0
T7	16667	16666	0	0
T13	29231	29230	0	0
T14	33610	33609	0	0
T44	14645	14644	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T79

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T79
1	1	Covered	T79

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T79
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	776	513	0	0
selKnown1	722	459	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	776	513	0	0
T8	2	1	0	0
T9	1	0	0	0
T15	1	0	0	0
T25	1	0	0	0
T31	1	0	0	0
T43	1	0	0	0
T46	2	1	0	0
T47	0	20	0	0
T48	0	4	0	0
T52	0	1	0	0
T57	1	0	0	0
T63	1	0	0	0
T75	0	1	0	0
T76	0	1	0	0
T79	1	0	0	0
T88	0	1	0	0
T92	0	10	0	0
T183	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	722	459	0	0
T16	1	0	0	0
T29	1	0	0	0
T30	1	0	0	0
T42	1	0	0	0
T45	1	0	0	0
T46	2	1	0	0
T47	0	20	0	0
T48	0	4	0	0
T49	1	0	0	0
T52	0	1	0	0
T75	1	0	0	0
T84	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T90	0	10	0	0
T91	1	0	0	0
T92	0	10	0	0
T100	1	0	0	0
T117	0	1	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T79

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T79
1	1	Covered	T79

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T79
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	5656779	5656296	0	0
selKnown1	5656778	5656295	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	5656779	5656296	0	0
T1	6387	6386	0	0
T2	579	578	0	0
T3	934	933	0	0
T4	323	322	0	0
T5	749	748	0	0
T6	3787	3786	0	0
T7	381	380	0	0
T13	901	900	0	0
T14	2030	2029	0	0
T44	1351	1350	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	5656778	5656295	0	0
T1	6387	6386	0	0
T2	579	578	0	0
T3	934	933	0	0
T4	323	322	0	0
T5	749	748	0	0
T6	3787	3786	0	0
T7	381	380	0	0
T13	901	900	0	0
T14	2030	2029	0	0
T44	1351	1350	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T79

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T79
1	1	Covered	T79

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T79
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1872	1389	0	0
selKnown1	1793	1310	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1872	1389	0	0
T8	2	1	0	0
T9	2	1	0	0
T15	1	0	0	0
T25	1	0	0	0
T31	1	0	0	0
T43	1	0	0	0
T46	2	1	0	0
T47	0	20	0	0
T48	0	5	0	0
T57	1	0	0	0
T63	1	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T79	2	1	0	0
T88	0	1	0	0
T183	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1793	1310	0	0
T16	1	0	0	0
T29	1	0	0	0
T30	1	0	0	0
T42	1	0	0	0
T45	1	0	0	0
T46	2	1	0	0
T47	0	20	0	0
T48	0	4	0	0
T49	1	0	0	0
T52	0	1	0	0
T75	1	0	0	0
T84	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T90	0	10	0	0
T91	1	0	0	0
T92	0	10	0	0
T100	1	0	0	0
T117	0	1	0	0