Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	262534	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

641241

1

T2

1

T3

1

T13

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	505122	1			T13	1		T19	2		T41	3
values[0x0]	175219	1			T3	1		T12	1		T13	1
values[0x1]	223434	1			T2	2		T3	2		T13	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	180430	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

723345

1

T2

1

T3

1

T13

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3907	1			T33	39		T68	21		T69	4
valid_sources[0x01]	3477	1			T61	2		T33	20		T68	22
valid_sources[0x02]	3885	1			T33	33		T68	28		T69	4
valid_sources[0x03]	2977	1			T33	30		T68	36		T69	4
valid_sources[0x04]	3917	1			T33	29		T68	19		T69	24
valid_sources[0x05]	3037	1			T61	2		T30	1		T33	28
valid_sources[0x06]	3742	1			T40	1		T33	24		T68	28
valid_sources[0x07]	3476	1			T33	24		T68	8		T25	42
valid_sources[0x08]	3158	1			T33	22		T68	22		T25	19
valid_sources[0x09]	3230	1			T61	1		T33	25		T68	19
valid_sources[0x0a]	3434	1			T33	15		T68	11		T25	36
valid_sources[0x0b]	4605	1			T50	1		T33	17		T68	18
valid_sources[0x0c]	4015	1			T54	1		T33	23		T68	23
valid_sources[0x0d]	3402	1			T33	20		T68	18		T69	64
valid_sources[0x0e]	3319	1			T57	9		T33	23		T68	27
valid_sources[0x0f]	4180	1			T6	2		T54	1		T33	24
valid_sources[0x10]	3076	1			T70	1		T33	25		T68	18
valid_sources[0x11]	3279	1			T33	10		T68	22		T69	94
valid_sources[0x12]	3605	1			T30	1		T33	40		T68	30
valid_sources[0x13]	3520	1			T19	1		T33	28		T68	25
valid_sources[0x14]	3542	1			T33	20		T68	21		T69	20
valid_sources[0x15]	3546	1			T65	1		T33	19		T68	18
valid_sources[0x16]	4227	1			T33	23		T68	23		T69	5
valid_sources[0x17]	3545	1			T9	1		T33	33		T68	22
valid_sources[0x18]	3132	1			T61	3		T33	18		T68	20
valid_sources[0x19]	3734	1			T33	19		T68	22		T25	32
valid_sources[0x1a]	3178	1			T92	1		T33	28		T68	18
valid_sources[0x1b]	3812	1			T39	1		T75	2		T33	18
valid_sources[0x1c]	3251	1			T33	33		T68	21		T69	17
valid_sources[0x1d]	3070	1			T33	27		T68	17		T69	15
valid_sources[0x1e]	6350	1			T87	1		T33	15		T68	17
valid_sources[0x1f]	3751	1			T61	1		T33	24		T68	15
valid_sources[0x20]	3837	1			T34	1		T33	26		T68	15
valid_sources[0x21]	3868	1			T33	19		T68	19		T25	37
valid_sources[0x22]	3621	1			T33	16		T68	23		T69	5
valid_sources[0x23]	3809	1			T33	25		T68	21		T25	28
valid_sources[0x24]	3574	1			T33	23		T68	24		T69	15
valid_sources[0x25]	3308	1			T58	1		T51	1		T236	1
valid_sources[0x26]	3809	1			T33	16		T68	15		T25	29
valid_sources[0x27]	2912	1			T33	27		T68	17		T69	8
valid_sources[0x28]	3322	1			T30	1		T72	2		T33	18
valid_sources[0x29]	3500	1			T33	20		T68	25		T69	11
valid_sources[0x2a]	3675	1			T33	13		T68	21		T69	17
valid_sources[0x2b]	3115	1			T61	2		T54	1		T33	25
valid_sources[0x2c]	2724	1			T32	1		T33	18		T68	22
valid_sources[0x2d]	4113	1			T33	28		T68	23		T69	7
valid_sources[0x2e]	3429	1			T33	27		T68	19		T69	32
valid_sources[0x2f]	3117	1			T33	14		T68	19		T25	30
valid_sources[0x30]	3577	1			T33	15		T68	13		T69	11
valid_sources[0x31]	3287	1			T61	1		T34	1		T33	25
valid_sources[0x32]	3753	1			T34	1		T33	23		T68	19
valid_sources[0x33]	3535	1			T61	2		T33	21		T68	20
valid_sources[0x34]	2842	1			T33	20		T68	16		T25	24
valid_sources[0x35]	3204	1			T33	22		T68	26		T69	4
valid_sources[0x36]	3452	1			T33	15		T68	14		T25	33
valid_sources[0x37]	3195	1			T33	28		T68	23		T25	35
valid_sources[0x38]	3796	1			T61	4		T237	2		T33	18
valid_sources[0x39]	3503	1			T33	30		T68	22		T69	5
valid_sources[0x3a]	3359	1			T54	1		T33	9		T68	22
valid_sources[0x3b]	3442	1			T33	24		T68	8		T25	24
valid_sources[0x3c]	3322	1			T33	17		T68	28		T69	7
valid_sources[0x3d]	3916	1			T2	2		T13	3		T33	32
valid_sources[0x3e]	3792	1			T30	1		T33	18		T68	33
valid_sources[0x3f]	3589	1			T33	19		T68	22		T69	45
valid_sources[0x40]	3704	1			T33	17		T68	32		T69	36
valid_sources[0x41]	3859	1			T33	25		T68	16		T25	21
valid_sources[0x42]	3193	1			T61	4		T33	17		T68	15
valid_sources[0x43]	3951	1			T33	19		T68	19		T25	32
valid_sources[0x44]	3051	1			T61	1		T33	21		T68	27
valid_sources[0x45]	3534	1			T33	25		T68	30		T69	14
valid_sources[0x46]	3556	1			T146	1		T55	4		T33	27
valid_sources[0x47]	3432	1			T3	1		T33	25		T68	13
valid_sources[0x48]	4238	1			T33	22		T68	21		T69	5
valid_sources[0x49]	3772	1			T189	1		T33	26		T68	18
valid_sources[0x4a]	3471	1			T33	29		T68	17		T69	3
valid_sources[0x4b]	3408	1			T41	1		T55	1		T189	1
valid_sources[0x4c]	2989	1			T61	5		T33	18		T68	23
valid_sources[0x4d]	3046	1			T59	1		T33	21		T68	18
valid_sources[0x4e]	3396	1			T56	1		T75	1		T33	19
valid_sources[0x4f]	3351	1			T33	26		T68	23		T25	36
valid_sources[0x50]	3010	1			T33	15		T68	19		T69	109
valid_sources[0x51]	3216	1			T51	1		T40	1		T138	2
valid_sources[0x52]	3580	1			T30	1		T33	19		T68	15
valid_sources[0x53]	2876	1			T61	1		T60	9		T33	42
valid_sources[0x54]	3514	1			T33	24		T68	21		T69	65
valid_sources[0x55]	3770	1			T33	31		T68	16		T25	18
valid_sources[0x56]	3292	1			T75	1		T33	31		T68	18
valid_sources[0x57]	3860	1			T51	1		T33	22		T68	18
valid_sources[0x58]	3120	1			T33	22		T68	24		T25	26
valid_sources[0x59]	3167	1			T206	3		T33	26		T68	22
valid_sources[0x5a]	3663	1			T42	6		T33	24		T68	32
valid_sources[0x5b]	2891	1			T33	32		T68	22		T25	28
valid_sources[0x5c]	3193	1			T61	7		T70	1		T33	21
valid_sources[0x5d]	3311	1			T61	2		T65	1		T33	40
valid_sources[0x5e]	3800	1			T33	27		T68	18		T69	51
valid_sources[0x5f]	3571	1			T61	3		T33	25		T68	18
valid_sources[0x60]	2953	1			T15	1		T82	2		T56	1
valid_sources[0x61]	3952	1			T33	37		T68	16		T69	20
valid_sources[0x62]	3096	1			T61	7		T33	21		T68	21
valid_sources[0x63]	3213	1			T9	1		T65	1		T33	23
valid_sources[0x64]	4072	1			T63	6		T33	15		T68	18
valid_sources[0x65]	3182	1			T33	15		T68	13		T69	7
valid_sources[0x66]	3583	1			T33	18		T68	20		T25	29
valid_sources[0x67]	3668	1			T189	3		T33	16		T68	21
valid_sources[0x68]	3214	1			T33	7		T68	16		T69	3
valid_sources[0x69]	3761	1			T9	1		T33	21		T68	19
valid_sources[0x6a]	3213	1			T14	1		T32	2		T33	9
valid_sources[0x6b]	3368	1			T60	2		T33	20		T68	21
valid_sources[0x6c]	3520	1			T51	1		T30	1		T33	23
valid_sources[0x6d]	3349	1			T61	3		T33	18		T68	13
valid_sources[0x6e]	3425	1			T40	1		T33	18		T68	12
valid_sources[0x6f]	3531	1			T33	12		T68	25		T69	17
valid_sources[0x70]	3253	1			T33	21		T68	16		T69	20
valid_sources[0x71]	3711	1			T33	26		T68	34		T69	9
valid_sources[0x72]	3363	1			T33	30		T68	23		T25	26
valid_sources[0x73]	4121	1			T33	15		T68	24		T69	2
valid_sources[0x74]	3777	1			T92	1		T33	22		T68	32
valid_sources[0x75]	3682	1			T33	26		T68	26		T69	10
valid_sources[0x76]	3910	1			T33	20		T68	22		T69	50
valid_sources[0x77]	3560	1			T33	16		T68	23		T69	4
valid_sources[0x78]	3872	1			T33	18		T68	24		T67	12
valid_sources[0x79]	3490	1			T33	25		T68	23		T69	14
valid_sources[0x7a]	4207	1			T33	16		T68	25		T69	31
valid_sources[0x7b]	3474	1			T58	1		T33	16		T68	28
valid_sources[0x7c]	3166	1			T30	1		T33	23		T68	27
valid_sources[0x7d]	2986	1			T146	1		T33	20		T68	21
valid_sources[0x7e]	3721	1			T33	14		T68	20		T25	33
valid_sources[0x7f]	3317	1			T55	1		T33	23		T68	23
valid_sources[0x80]	2848	1			T94	1		T33	19		T68	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

303559

1

T13

1

T19

2

T41

2

values[0x0]

all_enables

biggest_size

168652

1

T13

1

T6

1

T15

1

values[0x1]

all_enables

biggest_size

169030

1

T2

1

T3

1

T13

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

96409

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29211	1			T33	848		T68	796		T69	647
values[0x0]	36625	1			T2	1		T3	1		T12	1
values[0x1]	38351	1			T1	1		T14	1		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5166	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

99021

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	315	1			T59	1		T80	1		T33	10
valid_sources[0x01]	857	1			T47	2		T33	15		T68	12
valid_sources[0x02]	354	1			T143	2		T33	13		T68	10
valid_sources[0x03]	468	1			T33	9		T68	8		T69	13
valid_sources[0x04]	483	1			T65	1		T33	19		T68	9
valid_sources[0x05]	375	1			T22	2		T33	9		T68	11
valid_sources[0x06]	509	1			T46	16		T33	13		T68	11
valid_sources[0x07]	443	1			T33	15		T68	13		T69	14
valid_sources[0x08]	463	1			T19	1		T33	14		T68	5
valid_sources[0x09]	324	1			T33	14		T68	15		T69	6
valid_sources[0x0a]	396	1			T33	14		T68	17		T69	11
valid_sources[0x0b]	622	1			T33	11		T68	16		T69	10
valid_sources[0x0c]	297	1			T33	15		T68	20		T69	8
valid_sources[0x0d]	356	1			T33	4		T68	9		T69	16
valid_sources[0x0e]	311	1			T34	1		T238	1		T33	11
valid_sources[0x0f]	377	1			T33	14		T68	22		T69	6
valid_sources[0x10]	467	1			T33	13		T68	7		T69	14
valid_sources[0x11]	460	1			T239	13		T33	10		T68	15
valid_sources[0x12]	337	1			T33	19		T68	14		T69	9
valid_sources[0x13]	351	1			T65	1		T33	12		T68	3
valid_sources[0x14]	356	1			T51	1		T33	15		T68	10
valid_sources[0x15]	319	1			T4	1		T33	7		T68	16
valid_sources[0x16]	354	1			T240	1		T241	1		T33	18
valid_sources[0x17]	291	1			T240	1		T33	9		T68	8
valid_sources[0x18]	324	1			T242	1		T33	20		T68	15
valid_sources[0x19]	326	1			T33	11		T68	7		T69	6
valid_sources[0x1a]	301	1			T83	1		T136	1		T33	13
valid_sources[0x1b]	555	1			T33	14		T68	14		T69	12
valid_sources[0x1c]	481	1			T95	1		T33	12		T68	9
valid_sources[0x1d]	395	1			T33	17		T68	19		T69	13
valid_sources[0x1e]	719	1			T97	1		T33	13		T68	7
valid_sources[0x1f]	462	1			T33	13		T68	14		T69	5
valid_sources[0x20]	352	1			T33	14		T68	13		T69	9
valid_sources[0x21]	793	1			T33	9		T119	1		T68	14
valid_sources[0x22]	414	1			T33	11		T68	24		T69	10
valid_sources[0x23]	530	1			T33	11		T68	6		T69	14
valid_sources[0x24]	378	1			T118	1		T33	14		T68	13
valid_sources[0x25]	459	1			T22	1		T241	1		T33	11
valid_sources[0x26]	449	1			T201	1		T241	1		T33	14
valid_sources[0x27]	392	1			T33	9		T68	11		T69	8
valid_sources[0x28]	560	1			T33	18		T68	18		T69	10
valid_sources[0x29]	554	1			T30	1		T243	1		T33	13
valid_sources[0x2a]	410	1			T193	1		T33	16		T68	19
valid_sources[0x2b]	468	1			T143	1		T217	2		T33	5
valid_sources[0x2c]	329	1			T33	18		T68	17		T244	1
valid_sources[0x2d]	337	1			T33	6		T68	12		T179	2
valid_sources[0x2e]	278	1			T33	12		T68	6		T69	8
valid_sources[0x2f]	398	1			T33	10		T68	5		T178	5
valid_sources[0x30]	466	1			T53	1		T33	22		T68	9
valid_sources[0x31]	367	1			T5	1		T33	12		T68	13
valid_sources[0x32]	425	1			T33	9		T68	2		T69	17
valid_sources[0x33]	360	1			T33	19		T68	12		T69	9
valid_sources[0x34]	309	1			T33	13		T68	11		T69	8
valid_sources[0x35]	362	1			T145	1		T33	4		T68	9
valid_sources[0x36]	602	1			T33	16		T68	5		T69	10
valid_sources[0x37]	361	1			T33	10		T68	10		T69	8
valid_sources[0x38]	506	1			T237	1		T33	7		T68	14
valid_sources[0x39]	406	1			T54	1		T33	8		T68	13
valid_sources[0x3a]	398	1			T245	1		T33	11		T68	14
valid_sources[0x3b]	335	1			T62	1		T33	15		T68	18
valid_sources[0x3c]	312	1			T33	12		T68	14		T69	8
valid_sources[0x3d]	353	1			T40	2		T33	15		T68	12
valid_sources[0x3e]	348	1			T33	10		T68	15		T69	11
valid_sources[0x3f]	368	1			T192	2		T33	6		T68	14
valid_sources[0x40]	395	1			T44	2		T143	1		T217	1
valid_sources[0x41]	448	1			T87	1		T240	1		T33	14
valid_sources[0x42]	324	1			T189	1		T33	12		T68	19
valid_sources[0x43]	314	1			T33	20		T68	12		T69	11
valid_sources[0x44]	327	1			T33	8		T68	6		T69	11
valid_sources[0x45]	435	1			T20	1		T33	18		T68	11
valid_sources[0x46]	334	1			T33	19		T68	7		T69	6
valid_sources[0x47]	788	1			T34	4		T33	20		T68	12
valid_sources[0x48]	439	1			T33	10		T68	20		T69	15
valid_sources[0x49]	313	1			T89	1		T33	17		T68	10
valid_sources[0x4a]	352	1			T33	9		T68	11		T69	13
valid_sources[0x4b]	422	1			T14	1		T33	12		T68	10
valid_sources[0x4c]	359	1			T33	13		T68	6		T69	10
valid_sources[0x4d]	764	1			T33	11		T68	17		T69	18
valid_sources[0x4e]	266	1			T33	8		T68	8		T69	12
valid_sources[0x4f]	319	1			T246	15		T33	7		T68	7
valid_sources[0x50]	308	1			T33	8		T68	16		T69	6
valid_sources[0x51]	375	1			T33	16		T68	7		T69	10
valid_sources[0x52]	356	1			T245	1		T33	17		T68	12
valid_sources[0x53]	366	1			T47	1		T143	1		T33	12
valid_sources[0x54]	606	1			T58	1		T23	4		T33	9
valid_sources[0x55]	353	1			T92	1		T56	1		T33	12
valid_sources[0x56]	318	1			T33	10		T68	12		T69	7
valid_sources[0x57]	376	1			T194	1		T33	14		T68	14
valid_sources[0x58]	389	1			T82	1		T33	11		T68	11
valid_sources[0x59]	487	1			T40	2		T33	22		T68	18
valid_sources[0x5a]	405	1			T63	10		T33	15		T68	13
valid_sources[0x5b]	412	1			T33	17		T68	10		T69	17
valid_sources[0x5c]	764	1			T9	9		T86	1		T55	1
valid_sources[0x5d]	412	1			T33	13		T68	9		T69	14
valid_sources[0x5e]	424	1			T247	1		T33	5		T68	8
valid_sources[0x5f]	531	1			T33	18		T68	10		T69	12
valid_sources[0x60]	366	1			T71	1		T33	14		T68	13
valid_sources[0x61]	347	1			T50	1		T146	1		T33	12
valid_sources[0x62]	325	1			T33	14		T68	18		T69	16
valid_sources[0x63]	572	1			T66	1		T33	10		T68	11
valid_sources[0x64]	345	1			T65	1		T33	8		T68	24
valid_sources[0x65]	309	1			T43	1		T33	15		T68	8
valid_sources[0x66]	330	1			T33	23		T68	7		T69	16
valid_sources[0x67]	318	1			T32	1		T33	9		T68	13
valid_sources[0x68]	278	1			T40	1		T33	10		T68	19
valid_sources[0x69]	357	1			T33	16		T68	8		T67	3
valid_sources[0x6a]	317	1			T33	9		T68	6		T69	14
valid_sources[0x6b]	300	1			T39	1		T144	1		T33	11
valid_sources[0x6c]	299	1			T2	1		T7	1		T33	12
valid_sources[0x6d]	379	1			T65	1		T33	12		T68	14
valid_sources[0x6e]	469	1			T33	15		T68	19		T35	2
valid_sources[0x6f]	307	1			T144	1		T33	10		T68	12
valid_sources[0x70]	344	1			T33	12		T68	8		T69	4
valid_sources[0x71]	675	1			T33	8		T68	12		T69	14
valid_sources[0x72]	371	1			T33	10		T68	6		T69	10
valid_sources[0x73]	461	1			T33	18		T68	5		T69	15
valid_sources[0x74]	428	1			T33	9		T68	13		T69	9
valid_sources[0x75]	364	1			T80	1		T33	13		T68	12
valid_sources[0x76]	333	1			T33	16		T68	13		T69	9
valid_sources[0x77]	374	1			T33	12		T68	14		T69	7
valid_sources[0x78]	559	1			T241	1		T33	15		T68	5
valid_sources[0x79]	458	1			T33	14		T68	11		T69	15
valid_sources[0x7a]	407	1			T33	14		T68	13		T69	8
valid_sources[0x7b]	326	1			T64	1		T33	10		T68	14
valid_sources[0x7c]	396	1			T33	4		T68	9		T69	6
valid_sources[0x7d]	359	1			T248	1		T33	14		T68	10
valid_sources[0x7e]	582	1			T33	12		T68	12		T69	9
valid_sources[0x7f]	341	1			T76	1		T22	1		T33	10
valid_sources[0x80]	346	1			T240	1		T33	16		T68	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25502

1

T33

782

T68

757

T69

610

values[0x0]

all_enables

biggest_size

35554

1

T2

1

T3

1

T12

1

values[0x1]

all_enables

biggest_size

35353

1

T1

1

T14

1

T4

1