Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

646463

1

T2

1

T3

2

T12

1

full_word

655054

1

T2

1

T3

1

T13

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1301217	1			T2	2		T3	3		T12	1
auto[TlIntgErrCmd]	97	1			T181	7		T182	8		T183	8
auto[TlIntgErrData]	104	1			T181	8		T182	6		T183	6
auto[TlIntgErrBoth]	99	1			T181	5		T182	6		T183	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

522328

1

T13

1

T41

3

T15

1

auto[1]

779189

1

T2

2

T3

3

T12

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	217133	1			T41	1		T15	1		T58	4
auto[TlIntgErrNone]	partial	auto[1]	429053	1			T2	1		T3	2		T12	1
auto[TlIntgErrNone]	full_word	auto[0]	305057	1			T13	1		T41	2		T61	80
auto[TlIntgErrNone]	full_word	auto[1]	349974	1			T2	1		T3	1		T13	2
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T181	2		T182	3		T183	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T181	4		T182	5		T183	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T183	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T181	1		T231	1		T232	2
auto[TlIntgErrData]	partial	auto[0]	49	1			T181	2		T182	3		T183	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T181	4		T182	2		T183	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T181	2		T182	1		T183	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T183	1		T227	1		T231	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T182	2		T183	4		T227	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T181	4		T182	3		T183	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T181	1		T226	1		T233	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T182	1		T234	1		T229	1