Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	118884127	123081	0	0
late_debug_enable_rd_A	118884127	12651	0	0
late_debug_enable_regwen_rd_A	118884127	11224	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118884127	123081	0	0
T10	0	3941	0	0
T18	0	5392	0	0
T25	0	5966	0	0
T33	252767	5163	0	0
T35	52607	0	0	0
T68	233695	3826	0	0
T69	0	3707	0	0
T108	0	5315	0	0
T111	0	4173	0	0
T112	0	4260	0	0
T116	0	3940	0	0
T119	522255	0	0	0
T120	2037	0	0	0
T121	584648	0	0	0
T122	2724	0	0	0
T123	344902	0	0	0
T124	71915	0	0	0
T125	142552	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118884127	12651	0	0
T25	0	2290	0	0
T35	52607	0	0	0
T67	410008	0	0	0
T68	233695	1256	0	0
T69	0	636	0	0
T108	0	1282	0	0
T116	0	664	0	0
T121	584648	0	0	0
T122	2724	0	0	0
T123	344902	0	0	0
T124	71915	0	0	0
T125	142552	0	0	0
T128	0	28	0	0
T133	0	26	0	0
T175	0	41	0	0
T176	0	157	0	0
T177	0	110	0	0
T178	100833	0	0	0
T179	237685	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118884127	11224	0	0
T25	0	1988	0	0
T35	52607	0	0	0
T67	410008	0	0	0
T68	233695	1252	0	0
T69	0	522	0	0
T108	0	1176	0	0
T116	0	656	0	0
T121	584648	0	0	0
T122	2724	0	0	0
T123	344902	0	0	0
T124	71915	0	0	0
T125	142552	0	0	0
T128	0	38	0	0
T133	0	39	0	0
T175	0	23	0	0
T176	0	113	0	0
T177	0	51	0	0
T178	100833	0	0	0
T179	237685	0	0	0