Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T99
1	1	Covered	T99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T99
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	7626280	7624788	0	0
selKnown1	52247616	52246124	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	7626280	7624788	0	0
T1	6338	6336	0	0
T2	1836	1834	0	0
T3	2802	2800	0	0
T4	642	640	0	0
T5	1612	1610	0	0
T6	696	694	0	0
T7	4	2	0	0
T8	2	0	0	0
T9	0	12	0	0
T12	1158	1156	0	0
T13	1632	1630	0	0
T14	1738	1736	0	0
T16	3	1	0	0
T19	1288	1286	0	0
T20	14	12	0	0
T21	2	0	0	0
T37	2	0	0	0
T42	2	0	0	0
T43	0	4	0	0
T44	0	2	0	0
T48	0	40	0	0
T58	2	0	0	0
T61	2	0	0	0
T73	0	2	0	0
T80	0	2	0	0
T87	2	0	0	0
T89	0	1	0	0
T99	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	52247616	52246124	0	0
T1	67041	67039	0	0
T2	2549	2547	0	0
T3	15401	15399	0	0
T4	5055	5053	0	0
T5	11473	11471	0	0
T6	5229	5227	0	0
T9	0	8	0	0
T12	7242	7240	0	0
T13	66780	66778	0	0
T14	66017	66015	0	0
T19	12606	12604	0	0
T20	14	12	0	0
T21	2	0	0	0
T37	2	0	0	0
T42	2	0	0	0
T43	6	4	0	0
T44	0	2	0	0
T48	0	40	0	0
T49	0	2	0	0
T58	2	0	0	0
T61	2	0	0	0
T73	2	0	0	0
T80	0	2	0	0
T83	0	8	0	0
T84	0	20	0	0
T85	0	20	0	0
T87	2	0	0	0
T99	2	0	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T99
1	1	Covered	T99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T99
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2401900	2401637	0	0
selKnown1	47023316	47023053	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2401900	2401637	0	0
T1	3169	3168	0	0
T2	918	917	0	0
T3	1401	1400	0	0
T4	321	320	0	0
T5	806	805	0	0
T6	348	347	0	0
T12	579	578	0	0
T13	816	815	0	0
T14	869	868	0	0
T19	644	643	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	47023316	47023053	0	0
T1	63872	63871	0	0
T2	1631	1630	0	0
T3	14000	13999	0	0
T4	4734	4733	0	0
T5	10667	10666	0	0
T6	4881	4880	0	0
T12	6663	6662	0	0
T13	65964	65963	0	0
T14	65148	65147	0	0
T19	11962	11961	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T99
1	1	Covered	T99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T99
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	742	479	0	0
selKnown1	706	443	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	742	479	0	0
T7	2	1	0	0
T8	1	0	0	0
T9	0	6	0	0
T16	1	0	0	0
T20	7	6	0	0
T21	1	0	0	0
T37	1	0	0	0
T42	1	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T48	0	20	0	0
T58	1	0	0	0
T61	1	0	0	0
T73	0	1	0	0
T80	0	1	0	0
T83	0	4	0	0
T87	1	0	0	0
T89	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	706	443	0	0
T9	0	4	0	0
T20	7	6	0	0
T21	1	0	0	0
T37	1	0	0	0
T42	1	0	0	0
T43	3	2	0	0
T44	0	1	0	0
T48	0	20	0	0
T49	0	1	0	0
T58	1	0	0	0
T61	1	0	0	0
T73	1	0	0	0
T80	0	1	0	0
T83	0	4	0	0
T84	0	10	0	0
T85	0	10	0	0
T87	1	0	0	0
T99	1	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T99
1	1	Covered	T99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T99
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	5221941	5221458	0	0
selKnown1	5221940	5221457	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	5221941	5221458	0	0
T1	3169	3168	0	0
T2	918	917	0	0
T3	1401	1400	0	0
T4	321	320	0	0
T5	806	805	0	0
T6	348	347	0	0
T12	579	578	0	0
T13	816	815	0	0
T14	869	868	0	0
T19	644	643	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	5221940	5221457	0	0
T1	3169	3168	0	0
T2	918	917	0	0
T3	1401	1400	0	0
T4	321	320	0	0
T5	806	805	0	0
T6	348	347	0	0
T12	579	578	0	0
T13	816	815	0	0
T14	869	868	0	0
T19	644	643	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T99

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T99
1	1	Covered	T99

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T99
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1697	1214	0	0
selKnown1	1654	1171	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1697	1214	0	0
T7	2	1	0	0
T8	1	0	0	0
T9	0	6	0	0
T16	2	1	0	0
T20	7	6	0	0
T21	1	0	0	0
T37	1	0	0	0
T42	1	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T48	0	20	0	0
T58	1	0	0	0
T61	1	0	0	0
T73	0	1	0	0
T80	0	1	0	0
T87	1	0	0	0
T99	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1654	1171	0	0
T9	0	4	0	0
T20	7	6	0	0
T21	1	0	0	0
T37	1	0	0	0
T42	1	0	0	0
T43	3	2	0	0
T44	0	1	0	0
T48	0	20	0	0
T49	0	1	0	0
T58	1	0	0	0
T61	1	0	0	0
T73	1	0	0	0
T80	0	1	0	0
T83	0	4	0	0
T84	0	10	0	0
T85	0	10	0	0
T87	1	0	0	0
T99	1	0	0	0