Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	267662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

612053

1

T6

2

T45

3

T15

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	504010	1			T13	1		T45	3		T15	1
values[0x0]	161966	1			T2	1		T12	2		T13	2
values[0x1]	213739	1			T2	1		T3	1		T12	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	179902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

699813

1

T6

2

T45

4

T15

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2681	1			T60	18		T55	1		T27	11
valid_sources[0x01]	3440	1			T60	14		T71	1		T27	14
valid_sources[0x02]	2774	1			T60	13		T27	16		T9	2
valid_sources[0x03]	3315	1			T44	1		T60	13		T27	18
valid_sources[0x04]	4142	1			T60	15		T27	12		T9	31
valid_sources[0x05]	3778	1			T64	1		T60	14		T27	17
valid_sources[0x06]	2933	1			T61	1		T60	12		T27	17
valid_sources[0x07]	2968	1			T60	16		T27	20		T9	4
valid_sources[0x08]	3209	1			T54	1		T60	14		T27	27
valid_sources[0x09]	2845	1			T60	17		T27	13		T9	1
valid_sources[0x0a]	2947	1			T60	13		T145	1		T27	22
valid_sources[0x0b]	3845	1			T60	16		T27	16		T9	20
valid_sources[0x0c]	3260	1			T60	16		T27	21		T9	1
valid_sources[0x0d]	4478	1			T60	22		T27	14		T9	40
valid_sources[0x0e]	3696	1			T54	1		T60	15		T27	13
valid_sources[0x0f]	3026	1			T60	9		T27	9		T9	7
valid_sources[0x10]	3657	1			T60	12		T70	1		T27	13
valid_sources[0x11]	3424	1			T60	11		T27	15		T9	2
valid_sources[0x12]	3161	1			T60	18		T27	15		T9	6
valid_sources[0x13]	3743	1			T60	11		T55	1		T27	17
valid_sources[0x14]	3444	1			T64	3		T60	15		T71	1
valid_sources[0x15]	3256	1			T60	11		T27	18		T9	4
valid_sources[0x16]	3187	1			T13	3		T60	15		T27	17
valid_sources[0x17]	3047	1			T60	21		T27	21		T68	15
valid_sources[0x18]	3115	1			T30	1		T107	1		T60	21
valid_sources[0x19]	3752	1			T60	13		T27	12		T9	46
valid_sources[0x1a]	3385	1			T38	1		T60	17		T27	18
valid_sources[0x1b]	3170	1			T60	18		T27	22		T68	25
valid_sources[0x1c]	3087	1			T60	11		T27	16		T9	8
valid_sources[0x1d]	3254	1			T61	1		T60	11		T55	1
valid_sources[0x1e]	4059	1			T60	20		T27	17		T68	19
valid_sources[0x1f]	2988	1			T60	22		T27	15		T9	14
valid_sources[0x20]	3218	1			T14	1		T60	13		T70	1
valid_sources[0x21]	2959	1			T60	19		T27	18		T68	17
valid_sources[0x22]	3362	1			T60	18		T70	1		T27	16
valid_sources[0x23]	3170	1			T60	24		T27	16		T9	15
valid_sources[0x24]	3693	1			T60	12		T27	16		T9	2
valid_sources[0x25]	3517	1			T60	19		T27	19		T68	21
valid_sources[0x26]	3254	1			T60	16		T27	23		T9	16
valid_sources[0x27]	3029	1			T12	1		T60	18		T27	17
valid_sources[0x28]	3477	1			T60	13		T27	12		T9	2
valid_sources[0x29]	3230	1			T60	17		T27	20		T9	31
valid_sources[0x2a]	3643	1			T61	3		T30	1		T60	15
valid_sources[0x2b]	3487	1			T64	5		T60	12		T27	16
valid_sources[0x2c]	3555	1			T60	11		T27	14		T9	1
valid_sources[0x2d]	3279	1			T60	13		T99	1		T27	16
valid_sources[0x2e]	3280	1			T60	8		T55	1		T27	8
valid_sources[0x2f]	2903	1			T60	16		T27	15		T9	3
valid_sources[0x30]	3792	1			T60	17		T27	25		T9	1
valid_sources[0x31]	3184	1			T60	8		T27	9		T9	3
valid_sources[0x32]	3805	1			T60	14		T27	18		T9	24
valid_sources[0x33]	3526	1			T60	14		T27	13		T9	29
valid_sources[0x34]	3086	1			T60	10		T27	17		T9	3
valid_sources[0x35]	2686	1			T60	22		T27	12		T68	13
valid_sources[0x36]	3838	1			T60	21		T27	17		T9	2
valid_sources[0x37]	3761	1			T60	20		T27	19		T9	18
valid_sources[0x38]	3703	1			T60	18		T27	10		T9	8
valid_sources[0x39]	3571	1			T60	19		T27	18		T9	8
valid_sources[0x3a]	3225	1			T60	13		T27	16		T9	19
valid_sources[0x3b]	2688	1			T60	9		T27	12		T9	7
valid_sources[0x3c]	3763	1			T60	10		T210	2		T27	16
valid_sources[0x3d]	3146	1			T15	2		T106	1		T60	12
valid_sources[0x3e]	3178	1			T60	7		T99	1		T27	17
valid_sources[0x3f]	4486	1			T60	11		T146	2		T27	15
valid_sources[0x40]	4046	1			T60	11		T27	7		T9	11
valid_sources[0x41]	3590	1			T60	11		T27	18		T9	19
valid_sources[0x42]	3171	1			T61	3		T60	11		T27	14
valid_sources[0x43]	3085	1			T60	15		T27	14		T9	11
valid_sources[0x44]	3493	1			T60	8		T27	15		T9	11
valid_sources[0x45]	3650	1			T64	2		T60	15		T55	1
valid_sources[0x46]	3679	1			T60	12		T27	22		T9	7
valid_sources[0x47]	3282	1			T64	5		T60	19		T27	22
valid_sources[0x48]	2989	1			T92	2		T60	15		T27	10
valid_sources[0x49]	3668	1			T60	16		T27	12		T9	7
valid_sources[0x4a]	3550	1			T64	6		T60	10		T27	16
valid_sources[0x4b]	4363	1			T60	10		T27	16		T9	26
valid_sources[0x4c]	3768	1			T60	18		T27	17		T9	14
valid_sources[0x4d]	3522	1			T64	2		T60	19		T27	16
valid_sources[0x4e]	3612	1			T60	16		T27	17		T9	8
valid_sources[0x4f]	3276	1			T80	4		T60	14		T27	13
valid_sources[0x50]	3931	1			T38	2		T60	9		T27	12
valid_sources[0x51]	3337	1			T60	8		T27	11		T9	31
valid_sources[0x52]	3166	1			T60	16		T27	11		T9	4
valid_sources[0x53]	3529	1			T60	16		T55	1		T27	12
valid_sources[0x54]	2898	1			T61	1		T60	9		T27	16
valid_sources[0x55]	2917	1			T64	4		T60	13		T27	12
valid_sources[0x56]	3405	1			T2	1		T60	12		T27	15
valid_sources[0x57]	3714	1			T60	16		T27	20		T9	12
valid_sources[0x58]	3219	1			T60	13		T27	17		T9	5
valid_sources[0x59]	2998	1			T60	18		T27	15		T9	4
valid_sources[0x5a]	3232	1			T60	16		T27	9		T9	5
valid_sources[0x5b]	3220	1			T60	13		T27	16		T9	9
valid_sources[0x5c]	2566	1			T60	14		T27	9		T9	5
valid_sources[0x5d]	3695	1			T60	15		T27	17		T9	22
valid_sources[0x5e]	4111	1			T66	1		T60	6		T27	18
valid_sources[0x5f]	3377	1			T53	1		T60	16		T27	12
valid_sources[0x60]	2775	1			T30	1		T60	14		T27	13
valid_sources[0x61]	3053	1			T60	5		T27	22		T9	20
valid_sources[0x62]	3952	1			T60	14		T27	24		T9	8
valid_sources[0x63]	4051	1			T60	18		T27	12		T9	2
valid_sources[0x64]	3404	1			T60	19		T55	1		T27	16
valid_sources[0x65]	3121	1			T60	19		T27	20		T9	7
valid_sources[0x66]	2765	1			T60	18		T70	1		T71	1
valid_sources[0x67]	3044	1			T59	2		T60	14		T55	1
valid_sources[0x68]	2999	1			T60	11		T27	16		T68	16
valid_sources[0x69]	4110	1			T60	5		T27	11		T9	49
valid_sources[0x6a]	3448	1			T60	15		T27	14		T9	1
valid_sources[0x6b]	3429	1			T60	21		T27	8		T9	10
valid_sources[0x6c]	3862	1			T60	13		T27	10		T9	19
valid_sources[0x6d]	3268	1			T60	21		T27	18		T9	11
valid_sources[0x6e]	3273	1			T60	17		T27	10		T9	5
valid_sources[0x6f]	3181	1			T60	16		T27	15		T9	5
valid_sources[0x70]	2815	1			T60	13		T27	12		T9	14
valid_sources[0x71]	3311	1			T60	23		T27	13		T9	10
valid_sources[0x72]	3678	1			T66	1		T60	12		T27	12
valid_sources[0x73]	3358	1			T43	4		T60	21		T27	12
valid_sources[0x74]	3505	1			T54	1		T60	14		T27	24
valid_sources[0x75]	4232	1			T60	10		T27	17		T9	23
valid_sources[0x76]	3082	1			T60	15		T27	15		T9	11
valid_sources[0x77]	3306	1			T60	13		T27	10		T9	154
valid_sources[0x78]	3594	1			T60	11		T27	9		T9	9
valid_sources[0x79]	3640	1			T209	2		T60	13		T27	17
valid_sources[0x7a]	3052	1			T60	16		T27	9		T9	16
valid_sources[0x7b]	3381	1			T60	19		T27	17		T9	6
valid_sources[0x7c]	3063	1			T60	16		T27	12		T68	11
valid_sources[0x7d]	3127	1			T60	15		T27	10		T9	2
valid_sources[0x7e]	3577	1			T60	16		T27	20		T9	13
valid_sources[0x7f]	3186	1			T61	2		T60	24		T27	21
valid_sources[0x80]	3586	1			T60	14		T70	1		T27	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

302584

1

T45

3

T64

80

T61

3

values[0x0]

all_enables

biggest_size

154969

1

T209

1

T69

1

T60

425

values[0x1]

all_enables

biggest_size

154500

1

T6

2

T15

1

T91

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7887	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

101057

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30529	1			T60	507		T27	507		T9	498
values[0x0]	38062	1			T1	1		T3	1		T14	1
values[0x1]	40353	1			T2	1		T12	1		T13	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5067	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

103877

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	381	1			T60	11		T27	7		T9	9
valid_sources[0x01]	387	1			T44	1		T60	7		T27	10
valid_sources[0x02]	407	1			T60	5		T27	4		T9	11
valid_sources[0x03]	462	1			T60	8		T27	3		T9	5
valid_sources[0x04]	883	1			T60	7		T172	2		T27	6
valid_sources[0x05]	370	1			T175	1		T60	9		T238	1
valid_sources[0x06]	479	1			T60	10		T239	2		T27	9
valid_sources[0x07]	355	1			T31	1		T92	1		T60	7
valid_sources[0x08]	579	1			T60	6		T27	11		T9	17
valid_sources[0x09]	436	1			T60	8		T27	16		T9	13
valid_sources[0x0a]	382	1			T60	6		T27	5		T9	15
valid_sources[0x0b]	404	1			T60	9		T27	1		T9	13
valid_sources[0x0c]	444	1			T60	3		T27	1		T9	4
valid_sources[0x0d]	356	1			T60	4		T172	2		T27	18
valid_sources[0x0e]	314	1			T60	6		T9	14		T68	10
valid_sources[0x0f]	351	1			T60	10		T9	4		T68	19
valid_sources[0x10]	380	1			T100	1		T60	6		T27	9
valid_sources[0x11]	418	1			T60	8		T27	5		T9	6
valid_sources[0x12]	604	1			T78	1		T60	7		T240	2
valid_sources[0x13]	341	1			T100	1		T60	7		T57	1
valid_sources[0x14]	380	1			T60	1		T9	11		T68	3
valid_sources[0x15]	330	1			T98	1		T60	6		T9	10
valid_sources[0x16]	523	1			T60	4		T27	10		T9	17
valid_sources[0x17]	401	1			T46	5		T60	5		T97	1
valid_sources[0x18]	374	1			T20	1		T87	1		T103	1
valid_sources[0x19]	513	1			T60	6		T27	11		T204	2
valid_sources[0x1a]	529	1			T60	11		T27	5		T9	19
valid_sources[0x1b]	391	1			T60	6		T27	21		T9	1
valid_sources[0x1c]	436	1			T23	1		T143	1		T60	6
valid_sources[0x1d]	591	1			T60	9		T27	20		T9	3
valid_sources[0x1e]	387	1			T60	6		T27	9		T9	12
valid_sources[0x1f]	491	1			T13	1		T60	5		T27	27
valid_sources[0x20]	553	1			T60	8		T27	4		T9	9
valid_sources[0x21]	352	1			T100	1		T60	10		T27	26
valid_sources[0x22]	392	1			T60	7		T27	31		T9	20
valid_sources[0x23]	412	1			T60	8		T27	35		T9	17
valid_sources[0x24]	317	1			T60	8		T27	10		T9	10
valid_sources[0x25]	420	1			T60	10		T99	4		T146	1
valid_sources[0x26]	363	1			T60	8		T27	21		T9	1
valid_sources[0x27]	357	1			T60	11		T223	1		T241	1
valid_sources[0x28]	344	1			T60	3		T27	3		T9	7
valid_sources[0x29]	615	1			T209	1		T107	1		T60	11
valid_sources[0x2a]	346	1			T60	2		T27	7		T9	17
valid_sources[0x2b]	367	1			T60	5		T130	1		T27	11
valid_sources[0x2c]	456	1			T100	1		T60	3		T27	3
valid_sources[0x2d]	346	1			T106	1		T60	7		T238	1
valid_sources[0x2e]	402	1			T60	6		T27	28		T9	10
valid_sources[0x2f]	448	1			T1	1		T60	9		T27	1
valid_sources[0x30]	349	1			T60	9		T27	9		T9	3
valid_sources[0x31]	484	1			T60	5		T27	3		T9	9
valid_sources[0x32]	438	1			T60	19		T172	3		T27	1
valid_sources[0x33]	332	1			T100	1		T60	7		T27	2
valid_sources[0x34]	681	1			T60	8		T9	4		T68	44
valid_sources[0x35]	413	1			T60	10		T27	33		T9	7
valid_sources[0x36]	366	1			T174	1		T60	3		T27	6
valid_sources[0x37]	744	1			T3	1		T60	4		T27	11
valid_sources[0x38]	432	1			T59	1		T23	2		T60	9
valid_sources[0x39]	314	1			T60	5		T27	4		T9	6
valid_sources[0x3a]	375	1			T60	8		T27	21		T9	4
valid_sources[0x3b]	416	1			T60	4		T27	3		T9	13
valid_sources[0x3c]	388	1			T60	6		T27	16		T9	4
valid_sources[0x3d]	373	1			T60	3		T27	1		T9	7
valid_sources[0x3e]	430	1			T21	1		T80	1		T60	12
valid_sources[0x3f]	367	1			T60	6		T27	2		T9	13
valid_sources[0x40]	417	1			T60	14		T27	5		T9	11
valid_sources[0x41]	423	1			T43	1		T60	7		T129	2
valid_sources[0x42]	394	1			T60	6		T27	29		T9	6
valid_sources[0x43]	396	1			T60	11		T97	1		T27	17
valid_sources[0x44]	402	1			T60	8		T27	8		T9	13
valid_sources[0x45]	393	1			T60	7		T27	2		T9	2
valid_sources[0x46]	402	1			T23	1		T60	4		T172	1
valid_sources[0x47]	334	1			T60	7		T27	3		T9	3
valid_sources[0x48]	348	1			T60	7		T129	1		T27	1
valid_sources[0x49]	437	1			T67	1		T60	6		T27	27
valid_sources[0x4a]	491	1			T89	1		T60	9		T25	1
valid_sources[0x4b]	418	1			T60	8		T27	6		T9	12
valid_sources[0x4c]	432	1			T60	4		T27	10		T9	14
valid_sources[0x4d]	346	1			T60	7		T129	2		T25	1
valid_sources[0x4e]	388	1			T60	9		T27	2		T9	7
valid_sources[0x4f]	408	1			T125	1		T60	6		T221	1
valid_sources[0x50]	310	1			T60	11		T176	3		T27	5
valid_sources[0x51]	347	1			T51	9		T60	5		T57	1
valid_sources[0x52]	317	1			T60	5		T9	2		T18	22
valid_sources[0x53]	380	1			T60	7		T9	1		T242	2
valid_sources[0x54]	413	1			T60	8		T27	3		T9	5
valid_sources[0x55]	495	1			T50	1		T60	9		T27	32
valid_sources[0x56]	478	1			T102	1		T60	4		T9	8
valid_sources[0x57]	413	1			T52	1		T60	5		T55	1
valid_sources[0x58]	492	1			T76	1		T60	6		T27	12
valid_sources[0x59]	416	1			T60	6		T55	2		T27	9
valid_sources[0x5a]	643	1			T60	11		T27	3		T9	17
valid_sources[0x5b]	441	1			T60	7		T27	1		T9	24
valid_sources[0x5c]	337	1			T60	8		T27	5		T9	8
valid_sources[0x5d]	410	1			T60	13		T55	1		T27	21
valid_sources[0x5e]	950	1			T100	1		T60	7		T27	20
valid_sources[0x5f]	627	1			T12	1		T60	12		T27	11
valid_sources[0x60]	365	1			T60	7		T27	3		T9	6
valid_sources[0x61]	363	1			T50	1		T60	5		T239	2
valid_sources[0x62]	415	1			T60	6		T27	2		T9	4
valid_sources[0x63]	357	1			T60	2		T27	2		T9	3
valid_sources[0x64]	348	1			T60	6		T128	1		T27	11
valid_sources[0x65]	392	1			T60	12		T27	20		T9	11
valid_sources[0x66]	383	1			T60	8		T27	5		T9	9
valid_sources[0x67]	385	1			T60	7		T172	1		T27	2
valid_sources[0x68]	353	1			T60	12		T27	11		T9	8
valid_sources[0x69]	319	1			T60	5		T9	7		T68	11
valid_sources[0x6a]	404	1			T243	1		T60	10		T27	5
valid_sources[0x6b]	410	1			T60	11		T27	10		T9	5
valid_sources[0x6c]	677	1			T60	7		T97	1		T27	3
valid_sources[0x6d]	376	1			T60	3		T24	9		T9	18
valid_sources[0x6e]	282	1			T22	1		T60	9		T9	10
valid_sources[0x6f]	536	1			T60	6		T27	20		T9	3
valid_sources[0x70]	591	1			T60	6		T27	12		T9	7
valid_sources[0x71]	289	1			T60	5		T9	12		T68	7
valid_sources[0x72]	368	1			T100	1		T244	1		T60	9
valid_sources[0x73]	455	1			T60	4		T70	1		T145	1
valid_sources[0x74]	404	1			T26	1		T60	8		T132	1
valid_sources[0x75]	317	1			T60	6		T27	9		T9	1
valid_sources[0x76]	321	1			T60	6		T27	9		T9	1
valid_sources[0x77]	376	1			T52	1		T60	6		T27	5
valid_sources[0x78]	1016	1			T60	14		T27	9		T9	9
valid_sources[0x79]	317	1			T30	1		T60	5		T27	3
valid_sources[0x7a]	369	1			T100	1		T60	6		T27	24
valid_sources[0x7b]	485	1			T108	1		T60	8		T55	1
valid_sources[0x7c]	370	1			T60	9		T9	6		T245	2
valid_sources[0x7d]	322	1			T60	8		T27	4		T9	2
valid_sources[0x7e]	374	1			T101	1		T90	1		T60	13
valid_sources[0x7f]	459	1			T60	9		T27	6		T9	12
valid_sources[0x80]	285	1			T60	9		T9	1		T242	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26737

1

T60

468

T27

484

T9

469

values[0x0]

all_enables

biggest_size

37077

1

T1

1

T3

1

T14

1

values[0x1]

all_enables

biggest_size

37243

1

T2

1

T12

1

T13

1