Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

671443

1

T2

2

T3

1

T12

3

full_word

625744

1

T6

2

T45

3

T15

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1296857	1			T2	2		T3	1		T12	3
auto[TlIntgErrCmd]	107	1			T183	10		T184	5		T185	5
auto[TlIntgErrData]	114	1			T183	3		T184	1		T185	2
auto[TlIntgErrBoth]	109	1			T183	7		T184	4		T185	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

521187

1

T13

1

T45

3

T15

1

auto[1]

776000

1

T2

2

T3

1

T12

3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	216821	1			T13	1		T15	1		T61	7
auto[TlIntgErrNone]	partial	auto[1]	454310	1			T2	2		T3	1		T12	3
auto[TlIntgErrNone]	full_word	auto[0]	304218	1			T45	3		T64	80		T61	3
auto[TlIntgErrNone]	full_word	auto[1]	321508	1			T6	2		T15	1		T43	1
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T183	5		T184	2		T185	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T183	3		T184	3		T185	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T232	1		T233	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T183	2		T234	1		T235	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T183	1		T185	2		T178	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T183	2		T184	1		T178	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T230	2		T234	2		T233	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T236	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T183	1		T184	2		T185	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T183	6		T184	2		T185	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T237	1		T235	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T230	1		T232	1		T233	1