Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	119428661	130711	0	0
late_debug_enable_rd_A	119428661	3570	0	0
late_debug_enable_regwen_rd_A	119428661	3209	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119428661	130711	0	0
T9	0	2459	0	0
T18	0	5960	0	0
T24	116772	0	0	0
T27	0	2148	0	0
T57	193204	0	0	0
T60	116154	3032	0	0
T68	0	2831	0	0
T70	17739	0	0	0
T74	0	11171	0	0
T75	0	13986	0	0
T85	0	6288	0	0
T97	65954	0	0	0
T126	0	9638	0	0
T127	0	11029	0	0
T128	16878	0	0	0
T129	2032	0	0	0
T130	191990	0	0	0
T131	156463	0	0	0
T132	1140	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119428661	3570	0	0
T82	78170	477	0	0
T118	9132	28	0	0
T119	4149	25	0	0
T142	5649	1	0	0
T169	41848	45	0	0
T177	20330	107	0	0
T178	142591	49	0	0
T179	246195	167	0	0
T180	20001	62	0	0
T181	5553	51	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119428661	3209	0	0
T82	78170	533	0	0
T118	9132	4	0	0
T119	4149	13	0	0
T142	5649	2	0	0
T177	20330	104	0	0
T178	142591	37	0	0
T179	246195	122	0	0
T180	20001	57	0	0
T181	5553	34	0	0
T182	17410	5	0	0