Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T94

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T94
1	1	Covered	T94

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T94
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	7727037	7725545	0	0
selKnown1	63074725	63073233	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	7727037	7725545	0	0
T1	6014	6012	0	0
T2	1864	1862	0	0
T3	1094	1092	0	0
T4	3040	3038	0	0
T5	670	668	0	0
T6	652	650	0	0
T8	4	2	0	0
T12	2746	2744	0	0
T13	1456	1454	0	0
T14	1874	1872	0	0
T16	0	1	0	0
T20	2	0	0	0
T40	2	0	0	0
T43	0	4	0	0
T45	2910	2908	0	0
T46	11	9	0	0
T47	4	2	0	0
T48	0	40	0	0
T52	0	1	0	0
T61	2	0	0	0
T64	2	0	0	0
T77	4	2	0	0
T79	0	1	0	0
T91	2	0	0	0
T94	3	1	0	0
T98	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	63074725	63073233	0	0
T1	13330	13328	0	0
T2	4944	4942	0	0
T3	9751	9749	0	0
T4	30113	30111	0	0
T5	35436	35434	0	0
T6	3453	3451	0	0
T12	23016	23014	0	0
T13	8901	8899	0	0
T14	71471	71469	0	0
T16	2	0	0	0
T20	2	0	0	0
T21	2	0	0	0
T22	2	0	0	0
T29	2	0	0	0
T35	0	6	0	0
T42	2	0	0	0
T43	0	2	0	0
T45	22373	22371	0	0
T46	10	8	0	0
T47	4	2	0	0
T48	0	40	0	0
T52	0	2	0	0
T77	2	0	0	0
T86	0	2	0	0
T90	0	2	0	0
T94	2	0	0	0
T95	0	20	0	0
T96	0	20	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T94

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T94
1	1	Covered	T94

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T94
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2504626	2504363	0	0
selKnown1	57852410	57852147	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2504626	2504363	0	0
T1	3007	3006	0	0
T2	932	931	0	0
T3	547	546	0	0
T4	1520	1519	0	0
T5	335	334	0	0
T6	326	325	0	0
T12	1373	1372	0	0
T13	728	727	0	0
T14	937	936	0	0
T45	1455	1454	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	57852410	57852147	0	0
T1	10323	10322	0	0
T2	4012	4011	0	0
T3	9204	9203	0	0
T4	28593	28592	0	0
T5	35101	35100	0	0
T6	3127	3126	0	0
T12	21643	21642	0	0
T13	8173	8172	0	0
T14	70534	70533	0	0
T45	20918	20917	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T94

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T94
1	1	Covered	T94

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T94
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	795	532	0	0
selKnown1	758	495	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	795	532	0	0
T8	2	1	0	0
T20	1	0	0	0
T40	1	0	0	0
T43	0	2	0	0
T46	5	4	0	0
T47	2	1	0	0
T48	0	20	0	0
T52	0	1	0	0
T61	1	0	0	0
T64	1	0	0	0
T77	2	1	0	0
T78	0	1	0	0
T91	1	0	0	0
T94	1	0	0	0
T95	0	10	0	0
T98	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	758	495	0	0
T16	1	0	0	0
T20	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T29	1	0	0	0
T35	0	3	0	0
T42	1	0	0	0
T43	0	1	0	0
T46	5	4	0	0
T47	2	1	0	0
T48	0	20	0	0
T52	0	1	0	0
T77	1	0	0	0
T86	0	1	0	0
T90	0	1	0	0
T94	1	0	0	0
T95	0	10	0	0
T96	0	10	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T94

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T94
1	1	Covered	T94

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T94
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	5219790	5219307	0	0
selKnown1	5219790	5219307	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	5219790	5219307	0	0
T1	3007	3006	0	0
T2	932	931	0	0
T3	547	546	0	0
T4	1520	1519	0	0
T5	335	334	0	0
T6	326	325	0	0
T12	1373	1372	0	0
T13	728	727	0	0
T14	937	936	0	0
T45	1455	1454	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	5219790	5219307	0	0
T1	3007	3006	0	0
T2	932	931	0	0
T3	547	546	0	0
T4	1520	1519	0	0
T5	335	334	0	0
T6	326	325	0	0
T12	1373	1372	0	0
T13	728	727	0	0
T14	937	936	0	0
T45	1455	1454	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T94

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T94
1	1	Covered	T94

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T94
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1826	1343	0	0
selKnown1	1767	1284	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1826	1343	0	0
T8	2	1	0	0
T16	0	1	0	0
T20	1	0	0	0
T40	1	0	0	0
T43	0	2	0	0
T46	6	5	0	0
T47	2	1	0	0
T48	0	20	0	0
T61	1	0	0	0
T64	1	0	0	0
T77	2	1	0	0
T79	0	1	0	0
T91	1	0	0	0
T94	2	1	0	0
T98	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1767	1284	0	0
T16	1	0	0	0
T20	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T29	1	0	0	0
T35	0	3	0	0
T42	1	0	0	0
T43	0	1	0	0
T46	5	4	0	0
T47	2	1	0	0
T48	0	20	0	0
T52	0	1	0	0
T77	1	0	0	0
T86	0	1	0	0
T90	0	1	0	0
T94	1	0	0	0
T95	0	10	0	0
T96	0	10	0	0