Module Definition
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Module : prim_lc_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00
tb.dut.u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00
tb.dut.u_lc_en_sync_copies 100.00 100.00 100.00
tb.dut.u_pm_en_sync 100.00 100.00 100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync 100.00 100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync 100.00 100.00 100.00


Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_lc_en_sync_copies

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[3].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[4].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_pm_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.61 100.00 90.48 97.60 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[2].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00


Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.91 86.27 76.47 100.00 81.82 50.00 u_tlul_lc_gate_sba


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00


Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.00 100.00 100.00 100.00 100.00 50.00 u_tlul_lc_gate_rom


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORELINE
100.00 100.00
tb.dut.u_prim_lc_sync_lc_dft_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 
Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_lc_en_sync_copies

Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        5/5              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_pm_en_sync

Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        3/3              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORELINE
100.00 100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 
Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 1578 1578 0 0
OutputsKnown_A 346924223 346590431 0 0
gen_flops.OutputDelay_A 173557230 173383512 0 2367
gen_no_flops.OutputDelay_A 173366993 173200097 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1578 1578 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T12 6 6 0 0
T13 6 6 0 0
T14 6 6 0 0
T45 6 6 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 346924223 346590431 0 0
T1 61938 61542 0 0
T2 24072 23598 0 0
T3 55224 54810 0 0
T4 171558 171210 0 0
T5 210606 210138 0 0
T6 18762 18408 0 0
T12 129858 129552 0 0
T13 49038 48714 0 0
T14 423204 422814 0 0
T45 125508 125172 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 173557230 173383512 0 2367
T1 30969 30762 0 9
T2 12036 11790 0 9
T3 27612 27396 0 9
T4 85779 85596 0 9
T5 105303 105060 0 9
T6 9381 9195 0 9
T12 64929 64767 0 9
T13 24519 24348 0 9
T14 211602 211398 0 9
T45 62754 62577 0 9

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 173366993 173200097 0 0
T1 30969 30771 0 0
T2 12036 11799 0 0
T3 27612 27405 0 0
T4 85779 85605 0 0
T5 105303 105069 0 0
T6 9381 9204 0 0
T12 64929 64776 0 0
T13 24519 24357 0 0
T14 211602 211407 0 0
T45 62754 62586 0 0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 
Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 263 263 0 0
OutputsKnown_A 57852410 57796778 0 0
gen_flops.OutputDelay_A 57852410 57794504 0 789


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 263 263 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57796778 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57794504 0 789
T1 10323 10254 0 3
T2 4012 3930 0 3
T3 9204 9132 0 3
T4 28593 28532 0 3
T5 35101 35020 0 3
T6 3127 3065 0 3
T12 21643 21589 0 3
T13 8173 8116 0 3
T14 70534 70466 0 3
T45 20918 20859 0 3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 
Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 263 263 0 0
OutputsKnown_A 57852410 57796778 0 0
gen_flops.OutputDelay_A 57852410 57794504 0 789


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 263 263 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57796778 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57794504 0 789
T1 10323 10254 0 3
T2 4012 3930 0 3
T3 9204 9132 0 3
T4 28593 28532 0 3
T5 35101 35020 0 3
T6 3127 3065 0 3
T12 21643 21589 0 3
T13 8173 8116 0 3
T14 70534 70466 0 3
T45 20918 20859 0 3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies
Line No.TotalCoveredPercent
TOTAL66100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        5/5              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 263 263 0 0
OutputsKnown_A 57662173 57606541 0 0
gen_no_flops.OutputDelay_A 57662173 57606541 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 263 263 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57662173 57606541 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57662173 57606541 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0

Line Coverage for Instance : tb.dut.u_pm_en_sync
Line No.TotalCoveredPercent
TOTAL44100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        3/3              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
Assert Coverage for Instance : tb.dut.u_pm_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 263 263 0 0
OutputsKnown_A 57852410 57796778 0 0
gen_flops.OutputDelay_A 57852410 57794504 0 789


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 263 263 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57796778 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57794504 0 789
T1 10323 10254 0 3
T2 4012 3930 0 3
T3 9204 9132 0 3
T4 28593 28532 0 3
T5 35101 35020 0 3
T6 3127 3065 0 3
T12 21643 21589 0 3
T13 8173 8116 0 3
T14 70534 70466 0 3
T45 20918 20859 0 3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 263 263 0 0
OutputsKnown_A 57852410 57796778 0 0
gen_no_flops.OutputDelay_A 57852410 57796778 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 263 263 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57796778 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57796778 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS8400
CONT_ASSIGN9311100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00


83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 
Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
NumCopiesMustBeGreaterZero_A 263 263 0 0
OutputsKnown_A 57852410 57796778 0 0
gen_no_flops.OutputDelay_A 57852410 57796778 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 263 263 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T45 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57796778 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 57852410 57796778 0 0
T1 10323 10257 0 0
T2 4012 3933 0 0
T3 9204 9135 0 0
T4 28593 28535 0 0
T5 35101 35023 0 0
T6 3127 3068 0 0
T12 21643 21592 0 0
T13 8173 8119 0 0
T14 70534 70469 0 0
T45 20918 20862 0 0