Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	295345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

652858

1

T12

1

T48

7

T46

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	552185	1			T5	1		T48	10		T46	3
values[0x0]	170443	1			T12	1		T13	1		T14	1
values[0x1]	225575	1			T2	1		T12	1		T14	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

748565

1

T12

1

T14

1

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3340	1			T66	1		T64	16		T33	16
valid_sources[0x01]	3125	1			T67	1		T64	21		T33	19
valid_sources[0x02]	3591	1			T67	1		T64	26		T33	12
valid_sources[0x03]	3969	1			T232	2		T64	24		T33	17
valid_sources[0x04]	4079	1			T64	14		T33	22		T111	15
valid_sources[0x05]	3265	1			T64	33		T33	12		T111	55
valid_sources[0x06]	3808	1			T15	1		T64	25		T32	2
valid_sources[0x07]	3863	1			T64	27		T33	19		T17	5
valid_sources[0x08]	3336	1			T64	12		T33	14		T17	7
valid_sources[0x09]	4150	1			T72	1		T64	16		T33	18
valid_sources[0x0a]	3602	1			T12	2		T66	1		T64	23
valid_sources[0x0b]	3514	1			T61	1		T196	1		T64	31
valid_sources[0x0c]	3823	1			T66	1		T57	2		T64	17
valid_sources[0x0d]	3577	1			T195	1		T64	15		T33	30
valid_sources[0x0e]	3241	1			T64	28		T33	14		T17	4
valid_sources[0x0f]	4603	1			T196	3		T64	17		T33	15
valid_sources[0x10]	4101	1			T64	16		T33	19		T17	11
valid_sources[0x11]	4096	1			T57	1		T64	25		T33	22
valid_sources[0x12]	3198	1			T66	1		T64	14		T33	23
valid_sources[0x13]	3436	1			T72	1		T209	1		T57	1
valid_sources[0x14]	3424	1			T66	1		T67	2		T64	17
valid_sources[0x15]	3669	1			T67	2		T56	1		T64	24
valid_sources[0x16]	3882	1			T66	1		T195	1		T64	20
valid_sources[0x17]	3378	1			T66	1		T64	15		T33	15
valid_sources[0x18]	3558	1			T66	1		T64	22		T33	31
valid_sources[0x19]	3393	1			T48	1		T47	1		T64	17
valid_sources[0x1a]	3956	1			T64	24		T33	9		T17	10
valid_sources[0x1b]	3620	1			T64	22		T33	14		T17	7
valid_sources[0x1c]	3422	1			T67	1		T70	1		T64	23
valid_sources[0x1d]	3848	1			T64	17		T33	16		T17	4
valid_sources[0x1e]	3279	1			T57	1		T64	22		T33	23
valid_sources[0x1f]	3643	1			T66	1		T64	21		T33	17
valid_sources[0x20]	3795	1			T64	32		T33	19		T111	43
valid_sources[0x21]	3333	1			T64	27		T32	2		T33	18
valid_sources[0x22]	3210	1			T48	1		T64	22		T32	1
valid_sources[0x23]	4059	1			T35	1		T64	14		T33	31
valid_sources[0x24]	3500	1			T64	13		T33	21		T17	1
valid_sources[0x25]	3918	1			T67	3		T64	18		T33	20
valid_sources[0x26]	3524	1			T66	1		T47	2		T64	17
valid_sources[0x27]	3837	1			T48	1		T233	2		T64	16
valid_sources[0x28]	3218	1			T64	20		T33	22		T17	5
valid_sources[0x29]	3202	1			T64	19		T33	21		T17	16
valid_sources[0x2a]	3339	1			T64	17		T33	25		T111	103
valid_sources[0x2b]	3491	1			T64	18		T33	14		T17	1
valid_sources[0x2c]	3816	1			T44	2		T57	1		T37	8
valid_sources[0x2d]	4986	1			T56	1		T64	29		T33	21
valid_sources[0x2e]	3806	1			T66	2		T64	27		T33	21
valid_sources[0x2f]	3537	1			T64	20		T33	19		T111	60
valid_sources[0x30]	3222	1			T64	26		T33	32		T17	3
valid_sources[0x31]	3835	1			T48	1		T64	26		T33	18
valid_sources[0x32]	4058	1			T67	3		T64	22		T32	1
valid_sources[0x33]	3379	1			T64	19		T33	16		T17	41
valid_sources[0x34]	3748	1			T61	3		T64	16		T33	16
valid_sources[0x35]	3326	1			T64	13		T33	13		T17	2
valid_sources[0x36]	3104	1			T57	1		T64	20		T33	21
valid_sources[0x37]	3461	1			T57	1		T64	29		T33	11
valid_sources[0x38]	3318	1			T57	1		T64	15		T33	17
valid_sources[0x39]	3221	1			T66	2		T67	1		T59	2
valid_sources[0x3a]	3385	1			T72	1		T64	23		T33	18
valid_sources[0x3b]	3813	1			T30	1		T57	1		T64	29
valid_sources[0x3c]	3691	1			T66	1		T57	1		T64	24
valid_sources[0x3d]	3949	1			T64	27		T33	22		T17	115
valid_sources[0x3e]	3309	1			T62	8		T67	1		T72	1
valid_sources[0x3f]	3476	1			T67	2		T64	22		T33	20
valid_sources[0x40]	3635	1			T48	1		T8	1		T67	2
valid_sources[0x41]	3546	1			T64	17		T33	20		T17	146
valid_sources[0x42]	3569	1			T66	1		T64	28		T33	23
valid_sources[0x43]	3503	1			T64	24		T33	19		T111	37
valid_sources[0x44]	4097	1			T57	1		T64	18		T33	20
valid_sources[0x45]	3530	1			T67	1		T64	24		T33	12
valid_sources[0x46]	3455	1			T64	24		T33	13		T17	2
valid_sources[0x47]	3253	1			T67	1		T64	20		T33	22
valid_sources[0x48]	3050	1			T67	1		T64	21		T33	19
valid_sources[0x49]	3870	1			T65	1		T57	1		T64	19
valid_sources[0x4a]	3768	1			T70	1		T64	15		T33	13
valid_sources[0x4b]	4105	1			T14	1		T67	1		T64	12
valid_sources[0x4c]	4289	1			T66	2		T64	22		T32	1
valid_sources[0x4d]	4074	1			T64	27		T33	12		T17	4
valid_sources[0x4e]	6025	1			T66	1		T42	1		T44	1
valid_sources[0x4f]	3710	1			T66	1		T67	1		T64	18
valid_sources[0x50]	3732	1			T64	22		T33	22		T17	5
valid_sources[0x51]	3395	1			T195	1		T64	16		T33	17
valid_sources[0x52]	3772	1			T66	2		T65	2		T209	1
valid_sources[0x53]	3462	1			T66	2		T30	1		T70	2
valid_sources[0x54]	3174	1			T64	26		T33	20		T17	23
valid_sources[0x55]	3886	1			T68	7		T57	1		T64	22
valid_sources[0x56]	3956	1			T66	1		T93	1		T64	19
valid_sources[0x57]	3636	1			T135	2		T193	1		T64	19
valid_sources[0x58]	3212	1			T64	28		T33	16		T17	11
valid_sources[0x59]	3465	1			T66	1		T196	1		T64	14
valid_sources[0x5a]	3189	1			T64	19		T33	21		T17	5
valid_sources[0x5b]	3543	1			T67	1		T64	11		T33	17
valid_sources[0x5c]	3285	1			T64	18		T33	20		T17	17
valid_sources[0x5d]	3144	1			T56	1		T64	21		T33	10
valid_sources[0x5e]	3131	1			T2	1		T66	2		T64	25
valid_sources[0x5f]	3856	1			T66	2		T64	27		T33	15
valid_sources[0x60]	3137	1			T5	3		T67	2		T64	14
valid_sources[0x61]	3656	1			T64	13		T33	21		T17	3
valid_sources[0x62]	3396	1			T48	1		T67	3		T64	15
valid_sources[0x63]	3716	1			T193	1		T64	13		T33	19
valid_sources[0x64]	3564	1			T64	16		T33	17		T17	12
valid_sources[0x65]	3451	1			T66	2		T67	2		T234	2
valid_sources[0x66]	8403	1			T46	1		T64	18		T33	22
valid_sources[0x67]	3383	1			T57	1		T64	31		T33	10
valid_sources[0x68]	3418	1			T66	1		T64	25		T33	18
valid_sources[0x69]	3539	1			T66	1		T9	1		T67	1
valid_sources[0x6a]	3783	1			T66	2		T64	18		T33	18
valid_sources[0x6b]	3632	1			T48	1		T67	1		T193	1
valid_sources[0x6c]	3781	1			T64	18		T33	18		T17	8
valid_sources[0x6d]	4059	1			T42	1		T64	21		T33	15
valid_sources[0x6e]	7812	1			T66	1		T67	1		T64	14
valid_sources[0x6f]	3980	1			T8	1		T61	3		T64	11
valid_sources[0x70]	3876	1			T64	23		T33	26		T111	43
valid_sources[0x71]	3664	1			T63	9		T44	2		T64	12
valid_sources[0x72]	4407	1			T208	2		T72	1		T193	2
valid_sources[0x73]	4004	1			T66	1		T64	21		T33	15
valid_sources[0x74]	3985	1			T66	1		T67	2		T64	19
valid_sources[0x75]	3220	1			T46	1		T64	12		T33	16
valid_sources[0x76]	3565	1			T66	2		T67	2		T64	21
valid_sources[0x77]	3914	1			T57	1		T64	26		T33	20
valid_sources[0x78]	3257	1			T67	2		T57	1		T64	13
valid_sources[0x79]	5346	1			T64	19		T33	27		T17	13
valid_sources[0x7a]	3473	1			T66	3		T45	1		T64	25
valid_sources[0x7b]	3363	1			T64	21		T33	24		T111	35
valid_sources[0x7c]	4250	1			T57	1		T64	17		T33	21
valid_sources[0x7d]	3674	1			T44	2		T64	19		T33	22
valid_sources[0x7e]	3143	1			T64	13		T33	22		T111	26
valid_sources[0x7f]	3389	1			T64	15		T33	15		T111	36
valid_sources[0x80]	4168	1			T64	15		T33	20		T17	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

326611

1

T48

6

T46

1

T66

80

values[0x0]

all_enables

biggest_size

163172

1

T12

1

T48

1

T46

1

values[0x1]

all_enables

biggest_size

163075

1

T15

1

T42

1

T30

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8228	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

109847

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32709	1			T64	846		T33	828		T17	567
values[0x0]	41625	1			T3	1		T5	1		T21	1
values[0x1]	43741	1			T1	1		T2	1		T20	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5348	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

112727

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	301	1			T208	1		T64	9		T33	7
valid_sources[0x01]	548	1			T64	12		T33	21		T18	16
valid_sources[0x02]	419	1			T15	1		T64	14		T11	1
valid_sources[0x03]	507	1			T64	8		T33	1		T18	14
valid_sources[0x04]	320	1			T235	1		T64	16		T33	2
valid_sources[0x05]	715	1			T236	1		T64	16		T33	14
valid_sources[0x06]	282	1			T64	9		T18	11		T237	1
valid_sources[0x07]	391	1			T37	1		T238	1		T239	1
valid_sources[0x08]	351	1			T36	7		T37	1		T196	1
valid_sources[0x09]	312	1			T42	1		T64	11		T33	12
valid_sources[0x0a]	636	1			T64	11		T33	7		T177	1
valid_sources[0x0b]	334	1			T64	16		T33	1		T111	9
valid_sources[0x0c]	320	1			T64	7		T33	2		T18	13
valid_sources[0x0d]	420	1			T101	1		T64	8		T33	7
valid_sources[0x0e]	658	1			T64	11		T33	21		T111	1
valid_sources[0x0f]	428	1			T74	1		T56	1		T240	1
valid_sources[0x10]	833	1			T241	1		T196	1		T64	16
valid_sources[0x11]	647	1			T242	1		T64	11		T33	21
valid_sources[0x12]	368	1			T243	1		T64	14		T33	43
valid_sources[0x13]	366	1			T239	1		T64	5		T33	1
valid_sources[0x14]	459	1			T243	1		T57	1		T64	7
valid_sources[0x15]	332	1			T244	2		T210	1		T64	5
valid_sources[0x16]	436	1			T64	16		T218	2		T33	38
valid_sources[0x17]	525	1			T47	1		T23	1		T243	1
valid_sources[0x18]	543	1			T55	1		T64	13		T33	8
valid_sources[0x19]	386	1			T64	7		T117	18		T33	32
valid_sources[0x1a]	301	1			T4	1		T64	19		T18	21
valid_sources[0x1b]	410	1			T66	1		T64	9		T111	29
valid_sources[0x1c]	504	1			T245	1		T64	15		T33	1
valid_sources[0x1d]	904	1			T64	11		T33	13		T17	1
valid_sources[0x1e]	276	1			T212	1		T64	12		T18	12
valid_sources[0x1f]	574	1			T163	3		T239	1		T64	7
valid_sources[0x20]	458	1			T64	20		T33	6		T18	12
valid_sources[0x21]	280	1			T64	19		T33	16		T111	1
valid_sources[0x22]	833	1			T54	1		T64	4		T33	11
valid_sources[0x23]	522	1			T88	1		T64	13		T33	16
valid_sources[0x24]	416	1			T166	1		T164	3		T64	11
valid_sources[0x25]	399	1			T64	21		T33	25		T246	1
valid_sources[0x26]	381	1			T23	2		T247	7		T64	14
valid_sources[0x27]	596	1			T248	1		T64	16		T111	102
valid_sources[0x28]	335	1			T235	1		T64	11		T33	35
valid_sources[0x29]	421	1			T64	6		T33	1		T111	13
valid_sources[0x2a]	361	1			T64	9		T33	4		T18	15
valid_sources[0x2b]	751	1			T64	24		T33	2		T111	124
valid_sources[0x2c]	483	1			T64	22		T33	4		T177	1
valid_sources[0x2d]	936	1			T64	13		T33	52		T17	381
valid_sources[0x2e]	336	1			T35	1		T64	9		T33	5
valid_sources[0x2f]	339	1			T37	1		T64	13		T33	14
valid_sources[0x30]	319	1			T64	11		T33	1		T111	24
valid_sources[0x31]	306	1			T7	1		T64	7		T18	14
valid_sources[0x32]	575	1			T64	5		T33	18		T18	18
valid_sources[0x33]	619	1			T249	1		T244	3		T64	16
valid_sources[0x34]	552	1			T52	21		T64	13		T33	14
valid_sources[0x35]	663	1			T239	1		T64	24		T33	3
valid_sources[0x36]	365	1			T195	1		T64	14		T11	1
valid_sources[0x37]	420	1			T250	2		T57	1		T239	1
valid_sources[0x38]	392	1			T56	1		T60	1		T64	20
valid_sources[0x39]	420	1			T251	1		T250	3		T64	11
valid_sources[0x3a]	556	1			T64	13		T33	3		T111	1
valid_sources[0x3b]	663	1			T81	1		T64	12		T33	3
valid_sources[0x3c]	409	1			T64	14		T33	32		T18	20
valid_sources[0x3d]	385	1			T37	1		T64	12		T33	7
valid_sources[0x3e]	478	1			T64	7		T33	7		T252	1
valid_sources[0x3f]	554	1			T8	1		T64	4		T11	2
valid_sources[0x40]	418	1			T25	1		T64	24		T33	10
valid_sources[0x41]	335	1			T253	1		T64	16		T33	14
valid_sources[0x42]	417	1			T69	1		T64	9		T33	16
valid_sources[0x43]	286	1			T44	5		T64	12		T33	10
valid_sources[0x44]	545	1			T64	12		T33	1		T252	1
valid_sources[0x45]	310	1			T59	1		T241	2		T64	5
valid_sources[0x46]	291	1			T51	1		T64	11		T33	11
valid_sources[0x47]	553	1			T254	1		T255	1		T64	10
valid_sources[0x48]	573	1			T54	1		T256	1		T64	18
valid_sources[0x49]	361	1			T64	12		T33	4		T252	1
valid_sources[0x4a]	458	1			T64	11		T123	2		T33	12
valid_sources[0x4b]	337	1			T64	11		T33	25		T171	1
valid_sources[0x4c]	424	1			T64	6		T33	56		T205	1
valid_sources[0x4d]	436	1			T64	21		T18	12		T28	17
valid_sources[0x4e]	484	1			T209	1		T236	3		T64	7
valid_sources[0x4f]	300	1			T257	1		T64	10		T33	10
valid_sources[0x50]	484	1			T64	13		T33	6		T17	208
valid_sources[0x51]	375	1			T44	1		T99	1		T81	1
valid_sources[0x52]	338	1			T46	1		T64	15		T33	29
valid_sources[0x53]	307	1			T37	1		T258	1		T64	10
valid_sources[0x54]	533	1			T29	1		T83	2		T53	7
valid_sources[0x55]	604	1			T64	10		T33	4		T17	3
valid_sources[0x56]	345	1			T64	16		T33	23		T174	1
valid_sources[0x57]	479	1			T64	14		T111	1		T18	10
valid_sources[0x58]	797	1			T23	1		T64	8		T33	21
valid_sources[0x59]	1318	1			T239	1		T64	6		T111	113
valid_sources[0x5a]	466	1			T233	1		T64	14		T33	2
valid_sources[0x5b]	421	1			T9	1		T64	6		T33	1
valid_sources[0x5c]	345	1			T235	1		T64	8		T33	14
valid_sources[0x5d]	327	1			T196	1		T64	4		T33	12
valid_sources[0x5e]	638	1			T56	2		T259	1		T64	15
valid_sources[0x5f]	529	1			T13	1		T31	1		T64	15
valid_sources[0x60]	710	1			T135	1		T57	1		T64	13
valid_sources[0x61]	554	1			T78	1		T64	9		T118	1
valid_sources[0x62]	373	1			T57	1		T64	18		T33	6
valid_sources[0x63]	412	1			T250	1		T243	1		T64	17
valid_sources[0x64]	846	1			T260	10		T64	16		T33	46
valid_sources[0x65]	355	1			T235	1		T64	12		T33	14
valid_sources[0x66]	411	1			T64	11		T33	12		T18	10
valid_sources[0x67]	372	1			T76	1		T193	3		T235	1
valid_sources[0x68]	473	1			T261	1		T193	2		T64	7
valid_sources[0x69]	308	1			T64	8		T252	1		T111	1
valid_sources[0x6a]	902	1			T12	1		T61	1		T257	1
valid_sources[0x6b]	522	1			T64	8		T33	7		T17	2
valid_sources[0x6c]	443	1			T216	1		T183	4		T239	1
valid_sources[0x6d]	519	1			T56	1		T262	1		T183	4
valid_sources[0x6e]	347	1			T263	1		T64	12		T33	9
valid_sources[0x6f]	409	1			T64	17		T33	1		T17	1
valid_sources[0x70]	460	1			T81	1		T64	5		T111	2
valid_sources[0x71]	792	1			T2	1		T63	1		T64	13
valid_sources[0x72]	670	1			T64	10		T17	132		T18	15
valid_sources[0x73]	716	1			T20	1		T64	14		T33	1
valid_sources[0x74]	409	1			T64	12		T33	4		T111	123
valid_sources[0x75]	315	1			T64	20		T33	5		T111	1
valid_sources[0x76]	438	1			T5	1		T84	1		T264	1
valid_sources[0x77]	488	1			T72	1		T64	8		T123	3
valid_sources[0x78]	617	1			T57	1		T64	12		T18	17
valid_sources[0x79]	303	1			T265	1		T64	8		T18	18
valid_sources[0x7a]	450	1			T64	8		T111	104		T18	7
valid_sources[0x7b]	707	1			T64	16		T33	10		T111	233
valid_sources[0x7c]	468	1			T134	1		T64	19		T33	9
valid_sources[0x7d]	419	1			T41	1		T85	2		T242	1
valid_sources[0x7e]	607	1			T51	1		T64	14		T33	46
valid_sources[0x7f]	524	1			T62	1		T64	14		T33	19
valid_sources[0x80]	426	1			T23	1		T64	20		T33	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28793

1

T64

798

T33

801

T17

544

values[0x0]

all_enables

biggest_size

40565

1

T3

1

T5

1

T21

1

values[0x1]

all_enables

biggest_size

40489

1

T1

1

T2

1

T20

1