Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

730993

1

T2

1

T12

1

T13

1

full_word

667807

1

T12

1

T48

7

T46

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1398480	1			T2	1		T12	2		T13	1
auto[TlIntgErrCmd]	106	1			T181	6		T169	2		T182	7
auto[TlIntgErrData]	114	1			T181	8		T169	4		T182	7
auto[TlIntgErrBoth]	100	1			T181	6		T169	4		T182	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570858

1

T5

1

T48

10

T46

3

auto[1]

827942

1

T2

1

T12

2

T13

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	242517	1			T5	1		T48	4		T46	2
auto[TlIntgErrNone]	partial	auto[1]	488183	1			T2	1		T12	1		T13	1
auto[TlIntgErrNone]	full_word	auto[0]	328181	1			T48	6		T46	1		T66	80
auto[TlIntgErrNone]	full_word	auto[1]	339599	1			T12	1		T48	1		T46	1
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T181	2		T182	6		T224	6
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T181	3		T169	1		T182	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T181	1		T169	1		T227	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T224	1		T219	1		T228	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T181	3		T169	2		T182	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T181	2		T169	1		T182	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T181	3		T224	1		T222	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T169	1		T229	2		T230	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T181	3		T169	1		T182	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T181	3		T169	3		T182	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T182	1		T226	1		T227	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T226	1		T221	1		T231	1