Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.61	100.00	90.48	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	82880816	138320	0	0
late_debug_enable_rd_A	82880816	7720	0	0
late_debug_enable_regwen_rd_A	82880816	6099	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82880816	138320	0	0
T11	59533	0	0	0
T17	0	1964	0	0
T18	0	4221	0	0
T28	0	9625	0	0
T32	522934	0	0	0
T33	0	3037	0	0
T39	0	2499	0	0
T64	174488	3694	0	0
T73	0	9389	0	0
T82	0	13861	0	0
T107	0	10071	0	0
T111	0	9223	0	0
T117	12790	0	0	0
T118	31663	0	0	0
T119	179104	0	0	0
T120	226795	0	0	0
T121	202528	0	0	0
T122	36502	0	0	0
T123	1411	0	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82880816	7720	0	0
T17	128487	430	0	0
T18	0	1201	0	0
T111	239293	0	0	0
T113	0	5	0	0
T125	0	15	0	0
T128	0	8	0	0
T130	0	1	0	0
T153	0	931	0	0
T168	0	83	0	0
T169	0	30	0	0
T170	0	127	0	0
T171	4784	0	0	0
T172	467640	0	0	0
T173	24782	0	0	0
T174	103726	0	0	0
T175	565902	0	0	0
T176	656692	0	0	0
T177	3467	0	0	0
T178	488582	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82880816	6099	0	0
T17	128487	357	0	0
T18	0	1248	0	0
T111	239293	0	0	0
T113	0	1	0	0
T125	0	4	0	0
T128	0	3	0	0
T168	0	66	0	0
T169	0	49	0	0
T170	0	113	0	0
T171	4784	0	0	0
T172	467640	0	0	0
T173	24782	0	0	0
T174	103726	0	0	0
T175	565902	0	0	0
T176	656692	0	0	0
T177	3467	0	0	0
T178	488582	0	0	0
T179	0	214	0	0
T180	0	50	0	0