Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77
1	1	Covered	T77

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	6855502	6854010	0	0
selKnown1	46059796	46058304	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	6855502	6854010	0	0
T1	6640	6638	0	0
T2	1900	1898	0	0
T3	25840	25838	0	0
T4	740	738	0	0
T5	1578	1576	0	0
T6	2	1	0	0
T7	4	2	0	0
T8	2	0	0	0
T12	1758	1756	0	0
T13	1156	1154	0	0
T14	2866	2864	0	0
T15	2	0	0	0
T20	18700	18698	0	0
T21	10584	10582	0	0
T22	0	6	0	0
T25	1	0	0	0
T29	2	0	0	0
T49	2	2	0	0
T50	0	20	0	0
T54	0	2	0	0
T56	0	5	0	0
T62	2	0	0	0
T66	2	0	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	3	1	0	0
T88	2	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	46059796	46058304	0	0
T1	18378	18376	0	0
T2	4525	4523	0	0
T3	63270	63268	0	0
T4	4030	4028	0	0
T5	12022	12020	0	0
T12	5342	5340	0	0
T13	6843	6841	0	0
T14	60909	60907	0	0
T16	2	0	0	0
T20	47901	47899	0	0
T21	498025	498023	0	0
T22	8	6	0	0
T42	2	0	0	0
T44	0	6	0	0
T45	2	0	0	0
T49	4	2	0	0
T50	22	20	0	0
T51	2	0	0	0
T54	0	2	0	0
T56	0	8	0	0
T74	2	0	0	0
T83	0	2	0	0
T85	0	2	0	0
T89	0	20	0	0
T90	0	40	0	0
T96	2	0	0	0
T97	2	0	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77
1	1	Covered	T77

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2124478	2124215	0	0
selKnown1	41328871	41328608	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2124478	2124215	0	0
T1	3320	3319	0	0
T2	950	949	0	0
T3	12920	12919	0	0
T4	370	369	0	0
T5	789	788	0	0
T12	879	878	0	0
T13	578	577	0	0
T14	1433	1432	0	0
T20	9350	9349	0	0
T21	5292	5291	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	41328871	41328608	0	0
T1	15058	15057	0	0
T2	3575	3574	0	0
T3	50350	50349	0	0
T4	3660	3659	0	0
T5	11233	11232	0	0
T12	4463	4462	0	0
T13	6265	6264	0	0
T14	59476	59475	0	0
T20	38551	38550	0	0
T21	492733	492732	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77
1	1	Covered	T77

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	805	542	0	0
selKnown1	764	501	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	542	0	0
T7	2	1	0	0
T8	1	0	0	0
T15	1	0	0	0
T22	4	3	0	0
T29	1	0	0	0
T49	2	1	0	0
T50	0	10	0	0
T54	0	1	0	0
T56	0	5	0	0
T62	1	0	0	0
T66	1	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	1	0	0	0
T88	1	0	0	0
T89	0	10	0	0
T92	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	764	501	0	0
T16	1	0	0	0
T22	4	3	0	0
T42	1	0	0	0
T44	0	3	0	0
T45	1	0	0	0
T49	2	1	0	0
T50	11	10	0	0
T51	1	0	0	0
T54	0	1	0	0
T56	0	4	0	0
T74	1	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T89	0	10	0	0
T90	0	20	0	0
T96	1	0	0	0
T97	1	0	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77
1	1	Covered	T77

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4728403	4727920	0	0
selKnown1	4728402	4727919	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4728403	4727920	0	0
T1	3320	3319	0	0
T2	950	949	0	0
T3	12920	12919	0	0
T4	370	369	0	0
T5	789	788	0	0
T12	879	878	0	0
T13	578	577	0	0
T14	1433	1432	0	0
T20	9350	9349	0	0
T21	5292	5291	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	4728402	4727919	0	0
T1	3320	3319	0	0
T2	950	949	0	0
T3	12920	12919	0	0
T4	370	369	0	0
T5	789	788	0	0
T12	879	878	0	0
T13	578	577	0	0
T14	1433	1432	0	0
T20	9350	9349	0	0
T21	5292	5291	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77
1	1	Covered	T77

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T77
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1816	1333	0	0
selKnown1	1759	1276	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1816	1333	0	0
T6	2	1	0	0
T7	2	1	0	0
T8	1	0	0	0
T15	1	0	0	0
T22	0	3	0	0
T25	1	0	0	0
T29	1	0	0	0
T49	0	1	0	0
T50	0	10	0	0
T54	0	1	0	0
T62	1	0	0	0
T66	1	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	2	1	0	0
T88	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1759	1276	0	0
T16	1	0	0	0
T22	4	3	0	0
T42	1	0	0	0
T44	0	3	0	0
T45	1	0	0	0
T49	2	1	0	0
T50	11	10	0	0
T51	1	0	0	0
T54	0	1	0	0
T56	0	4	0	0
T74	1	0	0	0
T83	0	1	0	0
T85	0	1	0	0
T89	0	10	0	0
T90	0	20	0	0
T96	1	0	0	0
T97	1	0	0	0