Module Definition
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Module : prim_secded_inv_64_57_dec
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk 60.77 60.77
tb.dut.u_reg_regs.u_chk.u_chk 89.23 89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk 89.23 89.23


Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.77 60.77


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.77 60.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_rsp_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 89.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_cmd_intg_check.u_cmd_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[42:0] Yes Yes *T3,*T20,*T5 Yes T2,T20,T48 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T3,T20,T13 Yes T3,T20,T12 INPUT
data_o[56:0] Yes Yes T3,T20,T5 Yes T2,T20,T48 OUTPUT
syndrome_o[6:0] Yes Yes T20,T48,T7 Yes T20,T13,T48 OUTPUT
err_o[1:0] Yes Yes T2,T20,T12 Yes T20,T48,T8 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 158 60.77
Total Bits 0->1 130 79 60.77
Total Bits 1->0 130 79 60.77

Ports 4 3 75.00
Port Bits 260 158 60.77
Port Bits 0->1 130 79 60.77
Port Bits 1->0 130 79 60.77

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[5:0] Yes Yes *T3,*T20,*T46 Yes T20,T22,T87 INPUT
data_i[56:6] No No No INPUT
data_i[63:57] Yes Yes T3,T20,T22 Yes T3,T20,T12 INPUT
data_o[56:0] Yes Yes T3,T20,T46 Yes T20,T22,T87 OUTPUT
syndrome_o[6:0] Yes Yes T20,T22,T87 Yes T20,T8,T29 OUTPUT
err_o[1:0] Yes Yes T20,T22,T87 Yes T20,T8,T62 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[42:0] Yes Yes *T48,*T7,*T29 Yes T48,T7,T88 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T48,T88,T22 Yes T48,T74,T51 INPUT
data_o[56:0] Yes Yes T48,T7,T29 Yes T48,T7,T88 OUTPUT
syndrome_o[6:0] Yes Yes T48,T7,T88 Yes T48,T7,T88 OUTPUT
err_o[1:0] Yes Yes T48,T88,T29 Yes T48,T88,T29 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
TotalCoveredPercent
Totals 4 3 75.00
Total Bits 260 232 89.23
Total Bits 0->1 130 116 89.23
Total Bits 1->0 130 116 89.23

Ports 4 3 75.00
Port Bits 260 232 89.23
Port Bits 0->1 130 116 89.23
Port Bits 1->0 130 116 89.23

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[42:0] Yes Yes *T5,*T48,*T46 Yes T2,T20,T12 INPUT
data_i[56:43] No No No INPUT
data_i[63:57] Yes Yes T13,T14,T48 Yes T20,T13,T14 INPUT
data_o[56:0] Yes Yes T5,T48,T46 Yes T2,T20,T12 OUTPUT
syndrome_o[6:0] Yes Yes T15,T45,T47 Yes T20,T13,T15 OUTPUT
err_o[1:0] Yes Yes T2,T20,T12 Yes T15,T49,T45 OUTPUT

*Tests covering at least one bit in the range