Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	285589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

653647

1

T3

1

T7

2

T62

80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	555066	1			T3	1		T62	80		T13	1
values[0x0]	168223	1			T1	1		T2	2		T3	1
values[0x1]	215947	1			T2	1		T3	1		T31	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	195981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

743255

1

T2

1

T3

1

T7

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3448	1			T71	11		T34	21		T41	16
valid_sources[0x01]	3925	1			T74	1		T71	5		T34	39
valid_sources[0x02]	3678	1			T71	9		T41	15		T119	22
valid_sources[0x03]	3294	1			T74	1		T71	10		T34	11
valid_sources[0x04]	3268	1			T3	2		T46	2		T71	8
valid_sources[0x05]	3439	1			T47	1		T71	5		T34	20
valid_sources[0x06]	3368	1			T71	10		T41	20		T119	27
valid_sources[0x07]	3233	1			T46	4		T71	8		T34	31
valid_sources[0x08]	3956	1			T71	11		T48	1		T34	16
valid_sources[0x09]	3641	1			T74	2		T71	12		T34	16
valid_sources[0x0a]	3759	1			T62	3		T59	3		T71	8
valid_sources[0x0b]	3947	1			T59	3		T68	1		T71	8
valid_sources[0x0c]	3353	1			T62	4		T71	4		T41	24
valid_sources[0x0d]	3982	1			T71	7		T27	1		T34	5
valid_sources[0x0e]	4399	1			T62	15		T99	1		T71	8
valid_sources[0x0f]	3386	1			T71	12		T79	13		T34	18
valid_sources[0x10]	3003	1			T71	14		T34	10		T41	19
valid_sources[0x11]	3305	1			T74	1		T71	10		T34	14
valid_sources[0x12]	3452	1			T71	10		T41	20		T119	28
valid_sources[0x13]	3857	1			T47	1		T71	12		T34	1
valid_sources[0x14]	3484	1			T71	6		T34	1		T35	1
valid_sources[0x15]	3590	1			T71	9		T34	12		T41	20
valid_sources[0x16]	3654	1			T74	2		T71	8		T34	20
valid_sources[0x17]	3327	1			T71	7		T34	12		T35	1
valid_sources[0x18]	3397	1			T74	1		T71	9		T34	2
valid_sources[0x19]	3840	1			T71	8		T34	11		T41	22
valid_sources[0x1a]	3149	1			T63	1		T71	9		T34	2
valid_sources[0x1b]	3600	1			T26	1		T71	11		T34	9
valid_sources[0x1c]	3519	1			T71	7		T34	13		T39	1
valid_sources[0x1d]	3187	1			T71	15		T34	9		T41	15
valid_sources[0x1e]	3520	1			T71	13		T34	4		T41	25
valid_sources[0x1f]	3534	1			T71	8		T41	17		T119	27
valid_sources[0x20]	3810	1			T68	1		T71	15		T34	14
valid_sources[0x21]	3322	1			T74	1		T71	14		T34	16
valid_sources[0x22]	3964	1			T74	1		T46	2		T71	10
valid_sources[0x23]	3269	1			T45	2		T74	1		T71	11
valid_sources[0x24]	2843	1			T71	2		T48	1		T34	4
valid_sources[0x25]	3299	1			T13	1		T71	6		T34	2
valid_sources[0x26]	4599	1			T71	9		T34	1		T41	25
valid_sources[0x27]	4301	1			T71	11		T34	1		T41	24
valid_sources[0x28]	3198	1			T74	2		T71	3		T34	3
valid_sources[0x29]	3905	1			T71	14		T33	1		T34	2
valid_sources[0x2a]	3497	1			T71	6		T34	2		T41	17
valid_sources[0x2b]	3290	1			T71	6		T34	13		T41	17
valid_sources[0x2c]	2942	1			T62	9		T74	1		T70	1
valid_sources[0x2d]	3480	1			T71	5		T48	1		T34	5
valid_sources[0x2e]	3535	1			T10	3		T44	2		T71	6
valid_sources[0x2f]	3053	1			T71	9		T33	2		T34	5
valid_sources[0x30]	3905	1			T71	11		T48	1		T35	3
valid_sources[0x31]	3608	1			T68	2		T71	12		T34	38
valid_sources[0x32]	3571	1			T71	6		T219	1		T34	166
valid_sources[0x33]	3718	1			T71	11		T34	21		T41	13
valid_sources[0x34]	3431	1			T74	1		T72	1		T71	4
valid_sources[0x35]	3615	1			T71	11		T34	2		T41	11
valid_sources[0x36]	3930	1			T74	2		T71	8		T48	1
valid_sources[0x37]	4039	1			T74	1		T71	9		T34	68
valid_sources[0x38]	3760	1			T71	8		T34	6		T35	1
valid_sources[0x39]	3663	1			T91	1		T71	10		T34	40
valid_sources[0x3a]	4081	1			T71	9		T34	15		T41	17
valid_sources[0x3b]	3395	1			T74	3		T71	11		T34	22
valid_sources[0x3c]	3673	1			T71	4		T33	1		T34	12
valid_sources[0x3d]	3193	1			T71	10		T34	16		T41	23
valid_sources[0x3e]	3972	1			T71	12		T41	17		T119	16
valid_sources[0x3f]	3953	1			T71	13		T34	28		T41	17
valid_sources[0x40]	3535	1			T74	2		T70	1		T71	13
valid_sources[0x41]	3643	1			T71	7		T34	36		T41	33
valid_sources[0x42]	4370	1			T71	10		T34	1		T41	21
valid_sources[0x43]	4039	1			T62	5		T71	6		T34	3
valid_sources[0x44]	3683	1			T70	1		T71	10		T34	12
valid_sources[0x45]	3638	1			T71	12		T34	140		T41	14
valid_sources[0x46]	3392	1			T62	1		T71	6		T34	2
valid_sources[0x47]	3610	1			T71	6		T34	18		T41	25
valid_sources[0x48]	3581	1			T71	9		T34	20		T41	31
valid_sources[0x49]	3468	1			T74	2		T71	15		T34	16
valid_sources[0x4a]	3752	1			T71	9		T34	16		T41	19
valid_sources[0x4b]	3569	1			T71	11		T34	3		T41	14
valid_sources[0x4c]	3709	1			T2	1		T71	9		T67	2
valid_sources[0x4d]	3428	1			T71	8		T34	2		T41	14
valid_sources[0x4e]	3314	1			T71	4		T41	15		T119	18
valid_sources[0x4f]	4066	1			T74	1		T71	10		T34	4
valid_sources[0x50]	4108	1			T71	7		T143	1		T34	4
valid_sources[0x51]	3697	1			T74	1		T71	11		T34	5
valid_sources[0x52]	3585	1			T71	7		T34	4		T41	22
valid_sources[0x53]	3389	1			T71	4		T34	12		T41	19
valid_sources[0x54]	3357	1			T72	1		T71	7		T34	5
valid_sources[0x55]	3813	1			T74	3		T71	5		T34	10
valid_sources[0x56]	4416	1			T74	3		T71	5		T34	5
valid_sources[0x57]	3798	1			T2	1		T72	1		T71	13
valid_sources[0x58]	3493	1			T71	7		T34	5		T41	16
valid_sources[0x59]	3675	1			T71	7		T81	2		T34	11
valid_sources[0x5a]	3335	1			T71	5		T34	1		T41	24
valid_sources[0x5b]	3675	1			T71	16		T34	5		T41	23
valid_sources[0x5c]	3529	1			T62	2		T74	1		T71	15
valid_sources[0x5d]	3135	1			T74	1		T71	4		T34	14
valid_sources[0x5e]	3568	1			T59	3		T71	8		T33	1
valid_sources[0x5f]	2906	1			T71	7		T34	2		T41	22
valid_sources[0x60]	3463	1			T71	7		T34	9		T41	17
valid_sources[0x61]	3928	1			T71	4		T34	17		T41	18
valid_sources[0x62]	3930	1			T71	10		T34	1		T41	23
valid_sources[0x63]	3283	1			T71	7		T34	26		T41	17
valid_sources[0x64]	3345	1			T71	7		T34	9		T41	22
valid_sources[0x65]	3399	1			T71	14		T34	45		T41	16
valid_sources[0x66]	3575	1			T71	11		T34	4		T41	17
valid_sources[0x67]	4450	1			T63	1		T71	8		T48	1
valid_sources[0x68]	4215	1			T26	2		T74	3		T71	9
valid_sources[0x69]	4054	1			T71	5		T34	3		T41	21
valid_sources[0x6a]	3271	1			T4	1		T68	1		T71	9
valid_sources[0x6b]	4066	1			T71	1		T41	15		T119	32
valid_sources[0x6c]	3859	1			T74	1		T66	1		T71	10
valid_sources[0x6d]	4117	1			T71	9		T34	7		T41	13
valid_sources[0x6e]	3409	1			T62	5		T97	1		T71	7
valid_sources[0x6f]	4654	1			T71	10		T41	10		T119	38
valid_sources[0x70]	3728	1			T71	13		T34	24		T41	23
valid_sources[0x71]	4351	1			T71	9		T48	1		T34	19
valid_sources[0x72]	3210	1			T71	8		T41	23		T119	26
valid_sources[0x73]	3886	1			T47	1		T71	12		T34	7
valid_sources[0x74]	3427	1			T62	1		T74	1		T71	14
valid_sources[0x75]	3529	1			T71	7		T34	6		T41	15
valid_sources[0x76]	3778	1			T71	9		T16	1		T34	9
valid_sources[0x77]	3441	1			T66	1		T71	13		T34	6
valid_sources[0x78]	3087	1			T71	7		T34	28		T41	18
valid_sources[0x79]	4105	1			T62	1		T71	6		T34	23
valid_sources[0x7a]	3594	1			T74	2		T71	7		T33	2
valid_sources[0x7b]	3251	1			T71	7		T34	8		T41	17
valid_sources[0x7c]	3872	1			T71	12		T34	3		T35	1
valid_sources[0x7d]	3672	1			T74	1		T71	8		T34	7
valid_sources[0x7e]	3327	1			T71	10		T48	1		T34	7
valid_sources[0x7f]	3878	1			T74	2		T71	11		T34	5
valid_sources[0x80]	3232	1			T71	19		T41	20		T119	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

329752

1

T3

1

T62

80

T13

1

values[0x0]

all_enables

biggest_size

161841

1

T7

1

T13

1

T47

1

values[0x1]

all_enables

biggest_size

162054

1

T7

1

T69

1

T99

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8105	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

98011

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30506	1			T71	300		T75	1		T34	657
values[0x0]	36982	1			T3	1		T6	1		T31	1
values[0x1]	38628	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

100706

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	395	1			T86	2		T71	5		T34	9
valid_sources[0x01]	365	1			T71	4		T34	13		T41	6
valid_sources[0x02]	303	1			T71	1		T143	1		T34	12
valid_sources[0x03]	564	1			T71	4		T220	1		T34	8
valid_sources[0x04]	332	1			T71	5		T34	12		T41	7
valid_sources[0x05]	397	1			T14	1		T71	4		T12	1
valid_sources[0x06]	495	1			T71	6		T34	13		T41	12
valid_sources[0x07]	426	1			T71	6		T221	1		T34	10
valid_sources[0x08]	407	1			T71	5		T222	1		T223	1
valid_sources[0x09]	311	1			T71	2		T34	7		T41	8
valid_sources[0x0a]	377	1			T54	2		T71	6		T34	10
valid_sources[0x0b]	379	1			T71	7		T126	1		T34	7
valid_sources[0x0c]	308	1			T71	2		T205	1		T34	6
valid_sources[0x0d]	620	1			T63	1		T71	3		T34	6
valid_sources[0x0e]	361	1			T71	4		T48	10		T34	7
valid_sources[0x0f]	357	1			T71	4		T224	1		T34	19
valid_sources[0x10]	319	1			T60	1		T71	8		T34	12
valid_sources[0x11]	388	1			T71	2		T27	4		T24	1
valid_sources[0x12]	480	1			T72	1		T71	3		T78	1
valid_sources[0x13]	463	1			T52	1		T71	6		T225	1
valid_sources[0x14]	290	1			T98	1		T71	9		T34	8
valid_sources[0x15]	386	1			T71	6		T226	2		T34	11
valid_sources[0x16]	436	1			T71	3		T11	1		T34	13
valid_sources[0x17]	401	1			T71	3		T227	1		T34	11
valid_sources[0x18]	401	1			T105	1		T71	4		T219	1
valid_sources[0x19]	404	1			T10	1		T71	1		T34	16
valid_sources[0x1a]	372	1			T71	2		T80	1		T76	1
valid_sources[0x1b]	362	1			T71	1		T228	2		T34	9
valid_sources[0x1c]	471	1			T71	2		T229	1		T34	16
valid_sources[0x1d]	334	1			T71	8		T34	6		T41	12
valid_sources[0x1e]	383	1			T71	5		T128	1		T11	1
valid_sources[0x1f]	423	1			T71	5		T230	2		T34	12
valid_sources[0x20]	318	1			T71	3		T231	4		T34	8
valid_sources[0x21]	468	1			T71	5		T34	5		T41	10
valid_sources[0x22]	649	1			T123	1		T71	5		T172	1
valid_sources[0x23]	846	1			T71	7		T221	1		T34	8
valid_sources[0x24]	402	1			T71	5		T34	8		T41	14
valid_sources[0x25]	764	1			T71	8		T34	6		T41	12
valid_sources[0x26]	463	1			T44	1		T71	9		T34	7
valid_sources[0x27]	407	1			T71	3		T172	1		T232	1
valid_sources[0x28]	290	1			T71	4		T233	1		T229	1
valid_sources[0x29]	435	1			T71	3		T34	20		T41	8
valid_sources[0x2a]	343	1			T71	8		T234	1		T12	1
valid_sources[0x2b]	404	1			T71	4		T11	1		T34	10
valid_sources[0x2c]	384	1			T71	5		T227	1		T34	8
valid_sources[0x2d]	353	1			T71	2		T34	6		T41	9
valid_sources[0x2e]	362	1			T71	5		T34	8		T41	12
valid_sources[0x2f]	383	1			T71	6		T11	1		T34	5
valid_sources[0x30]	372	1			T92	1		T71	1		T34	14
valid_sources[0x31]	327	1			T71	3		T34	8		T41	7
valid_sources[0x32]	459	1			T71	5		T34	10		T41	18
valid_sources[0x33]	362	1			T71	6		T226	1		T34	14
valid_sources[0x34]	417	1			T104	1		T71	5		T230	3
valid_sources[0x35]	441	1			T2	1		T71	4		T34	6
valid_sources[0x36]	360	1			T71	1		T34	7		T41	18
valid_sources[0x37]	445	1			T73	1		T71	6		T227	1
valid_sources[0x38]	287	1			T71	7		T34	2		T41	10
valid_sources[0x39]	749	1			T51	1		T71	4		T12	1
valid_sources[0x3a]	494	1			T71	11		T229	1		T34	4
valid_sources[0x3b]	376	1			T71	2		T126	2		T78	1
valid_sources[0x3c]	346	1			T71	5		T34	6		T41	5
valid_sources[0x3d]	382	1			T71	8		T75	2		T235	12
valid_sources[0x3e]	483	1			T71	3		T34	7		T41	14
valid_sources[0x3f]	362	1			T71	4		T34	10		T178	1
valid_sources[0x40]	412	1			T62	1		T45	1		T71	5
valid_sources[0x41]	437	1			T71	1		T34	7		T41	7
valid_sources[0x42]	355	1			T71	5		T34	9		T41	15
valid_sources[0x43]	455	1			T71	8		T34	12		T41	8
valid_sources[0x44]	367	1			T71	3		T11	1		T34	7
valid_sources[0x45]	270	1			T52	5		T71	5		T84	1
valid_sources[0x46]	584	1			T71	3		T34	10		T179	1
valid_sources[0x47]	388	1			T71	4		T34	14		T41	7
valid_sources[0x48]	313	1			T71	3		T236	1		T34	18
valid_sources[0x49]	342	1			T71	2		T205	1		T34	12
valid_sources[0x4a]	376	1			T71	7		T34	8		T41	5
valid_sources[0x4b]	389	1			T71	6		T34	10		T41	16
valid_sources[0x4c]	315	1			T71	2		T34	8		T181	1
valid_sources[0x4d]	462	1			T71	6		T34	15		T41	12
valid_sources[0x4e]	396	1			T71	3		T34	8		T41	7
valid_sources[0x4f]	466	1			T51	1		T71	3		T236	1
valid_sources[0x50]	321	1			T71	4		T34	9		T177	2
valid_sources[0x51]	372	1			T26	5		T71	2		T34	17
valid_sources[0x52]	434	1			T71	7		T34	8		T182	1
valid_sources[0x53]	872	1			T71	2		T78	1		T34	13
valid_sources[0x54]	474	1			T46	1		T71	6		T236	1
valid_sources[0x55]	293	1			T71	4		T221	1		T34	5
valid_sources[0x56]	424	1			T71	3		T205	2		T34	12
valid_sources[0x57]	267	1			T71	4		T34	9		T194	4
valid_sources[0x58]	322	1			T71	6		T34	8		T41	9
valid_sources[0x59]	453	1			T71	4		T229	1		T34	9
valid_sources[0x5a]	374	1			T8	1		T203	1		T71	4
valid_sources[0x5b]	331	1			T26	1		T71	7		T34	6
valid_sources[0x5c]	340	1			T71	5		T27	3		T75	2
valid_sources[0x5d]	385	1			T71	4		T227	1		T34	12
valid_sources[0x5e]	348	1			T71	2		T11	1		T33	2
valid_sources[0x5f]	353	1			T71	3		T34	19		T41	11
valid_sources[0x60]	353	1			T71	8		T34	11		T41	15
valid_sources[0x61]	477	1			T71	10		T204	1		T34	9
valid_sources[0x62]	407	1			T21	1		T46	1		T237	1
valid_sources[0x63]	321	1			T90	2		T71	4		T172	1
valid_sources[0x64]	425	1			T71	1		T226	1		T34	15
valid_sources[0x65]	340	1			T71	5		T172	1		T34	11
valid_sources[0x66]	310	1			T71	3		T34	10		T238	1
valid_sources[0x67]	447	1			T71	2		T24	3		T34	10
valid_sources[0x68]	373	1			T71	5		T239	1		T34	7
valid_sources[0x69]	418	1			T49	2		T104	2		T71	2
valid_sources[0x6a]	353	1			T71	8		T34	12		T41	13
valid_sources[0x6b]	414	1			T71	3		T229	1		T79	3
valid_sources[0x6c]	555	1			T122	1		T71	3		T33	3
valid_sources[0x6d]	475	1			T53	3		T71	10		T34	6
valid_sources[0x6e]	383	1			T71	6		T221	2		T34	7
valid_sources[0x6f]	466	1			T71	3		T205	1		T34	9
valid_sources[0x70]	379	1			T71	3		T75	4		T34	7
valid_sources[0x71]	381	1			T71	4		T34	6		T41	13
valid_sources[0x72]	389	1			T71	6		T240	9		T34	16
valid_sources[0x73]	632	1			T71	3		T34	14		T41	9
valid_sources[0x74]	447	1			T32	1		T46	1		T22	5
valid_sources[0x75]	316	1			T71	6		T34	11		T41	9
valid_sources[0x76]	492	1			T31	1		T87	1		T71	1
valid_sources[0x77]	375	1			T71	4		T228	1		T34	13
valid_sources[0x78]	518	1			T71	1		T34	6		T41	7
valid_sources[0x79]	319	1			T71	5		T23	1		T34	7
valid_sources[0x7a]	345	1			T20	1		T71	5		T241	1
valid_sources[0x7b]	389	1			T30	1		T91	1		T71	7
valid_sources[0x7c]	393	1			T46	1		T22	3		T71	4
valid_sources[0x7d]	465	1			T71	6		T34	9		T41	7
valid_sources[0x7e]	337	1			T71	1		T16	1		T34	15
valid_sources[0x7f]	390	1			T104	1		T71	3		T228	5
valid_sources[0x80]	413	1			T71	4		T34	13		T41	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26286

1

T71

284

T34

625

T41

661

values[0x0]

all_enables

biggest_size

35986

1

T3

1

T6

1

T31

1

values[0x1]

all_enables

biggest_size

35739

1

T1

1

T2

1

T4

1