Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

654927

1

T1

1

T2

3

T3

2

full_word

666606

1

T3

1

T7

2

T62

80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1321211	1			T1	1		T2	3		T3	3
auto[TlIntgErrCmd]	115	1			T174	8		T208	5		T206	3
auto[TlIntgErrData]	96	1			T94	1		T174	6		T206	2
auto[TlIntgErrBoth]	111	1			T93	1		T174	6		T208	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570854

1

T3

1

T62

80

T13

1

auto[1]

750679

1

T1

1

T2

3

T3

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	239554	1			T59	6		T47	1		T69	7
auto[TlIntgErrNone]	partial	auto[1]	415077	1			T1	1		T2	3		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	331147	1			T3	1		T62	80		T13	1
auto[TlIntgErrNone]	full_word	auto[1]	335433	1			T7	2		T13	1		T47	1
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T174	2		T206	1		T207	3
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T174	6		T208	5		T206	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T212	1		T213	1		T214	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T207	1		T212	2		T215	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T174	3		T206	2		T207	5
auto[TlIntgErrData]	partial	auto[1]	29	1			T94	1		T174	2		T207	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T207	1		T216	1		T217	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T174	1		T207	1		T213	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T93	1		T174	2		T208	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T174	4		T208	2		T206	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T216	1		T213	1		T218	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T208	1		T207	1		-	-