Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.57	100.00	95.24	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	112886363	116369	0	0
late_debug_enable_rd_A	112886363	17515	0	0
late_debug_enable_regwen_rd_A	112886363	15308	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112886363	116369	0	0
T11	141943	0	0	0
T18	0	4881	0	0
T23	345759	0	0	0
T27	218694	0	0	0
T34	0	2863	0	0
T41	0	3295	0	0
T64	0	10435	0	0
T67	12593	0	0	0
T71	61175	1188	0	0
T80	14945	0	0	0
T83	0	10188	0	0
T85	0	7174	0	0
T93	0	1	0	0
T119	0	4389	0	0
T125	74921	0	0	0
T126	682	0	0	0
T127	298545	0	0	0
T128	39086	0	0	0
T175	0	1	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112886363	17515	0	0
T18	0	2237	0	0
T34	155217	1111	0	0
T35	97338	0	0	0
T65	0	2636	0	0
T83	0	1949	0	0
T120	0	28	0	0
T132	0	8	0	0
T133	0	4	0	0
T138	0	236	0	0
T174	0	69	0	0
T176	0	984	0	0
T177	648062	0	0	0
T178	36289	0	0	0
T179	225935	0	0	0
T180	7811	0	0	0
T181	104522	0	0	0
T182	45834	0	0	0
T183	74865	0	0	0
T184	999180	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112886363	15308	0	0
T18	0	2003	0	0
T34	155217	1024	0	0
T35	97338	0	0	0
T65	0	2283	0	0
T83	0	1655	0	0
T120	0	7	0	0
T132	0	3	0	0
T133	0	4	0	0
T138	0	230	0	0
T174	0	82	0	0
T176	0	792	0	0
T177	648062	0	0	0
T178	36289	0	0	0
T179	225935	0	0	0
T180	7811	0	0	0
T181	104522	0	0	0
T182	45834	0	0	0
T183	74865	0	0	0
T184	999180	0	0	0