Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48
1	1	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T58,T11,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	7443080	7441600	0	0
selKnown1	55406055	55404575	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	7443080	7441600	0	0
T1	1892	1890	0	0
T2	2746	2744	0	0
T3	1492	1490	0	0
T4	1172	1170	0	0
T5	650	648	0	0
T6	720	718	0	0
T7	724	720	0	0
T8	4	2	0	0
T9	4	2	0	0
T13	2	0	0	0
T14	0	1	0	0
T19	30730	30726	0	0
T25	1386	1382	0	0
T26	0	5	0	0
T29	2	0	0	0
T31	2038	2036	0	0
T49	0	2	0	0
T50	0	40	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	3	1	0	0
T62	2	0	0	0
T92	2	0	0	0
T185	0	2	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	55406055	55404575	0	0
T1	18862	18860	0	0
T2	67818	67816	0	0
T3	7254	7252	0	0
T4	10029	10027	0	0
T5	16502	16500	0	0
T6	35438	35436	0	0
T7	3749	3745	0	0
T8	2	0	0	0
T9	2	0	0	0
T13	2	0	0	0
T19	92614	92610	0	0
T25	3656	3652	0	0
T26	0	4	0	0
T29	2	0	0	0
T31	42267	42265	0	0
T49	0	2	0	0
T50	0	40	0	0
T54	0	2	0	0
T58	2	0	0	0
T62	2	0	0	0
T86	0	2	0	0
T90	0	2	0	0
T92	2	0	0	0
T95	0	20	0	0
T96	0	40	0	0
T101	0	40	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48
1	1	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T58,T11,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	2269509	2269249	0	0
selKnown1	50232646	50232386	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	2269509	2269249	0	0
T1	946	945	0	0
T2	1373	1372	0	0
T3	746	745	0	0
T4	586	585	0	0
T5	325	324	0	0
T6	360	359	0	0
T7	361	360	0	0
T19	15359	15358	0	0
T25	692	691	0	0
T31	1019	1018	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	50232646	50232386	0	0
T1	17916	17915	0	0
T2	66445	66444	0	0
T3	6508	6507	0	0
T4	9443	9442	0	0
T5	16177	16176	0	0
T6	35078	35077	0	0
T7	3386	3385	0	0
T19	77243	77242	0	0
T25	2962	2961	0	0
T31	41248	41247	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48
1	1	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T58,T11,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	809	549	0	0
selKnown1	759	499	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	809	549	0	0
T7	1	0	0	0
T8	2	1	0	0
T9	2	1	0	0
T13	1	0	0	0
T19	6	5	0	0
T25	1	0	0	0
T26	0	2	0	0
T29	1	0	0	0
T49	0	1	0	0
T50	0	20	0	0
T54	0	1	0	0
T55	0	1	0	0
T58	1	0	0	0
T62	1	0	0	0
T92	1	0	0	0
T95	0	10	0	0
T185	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	759	499	0	0
T7	1	0	0	0
T8	1	0	0	0
T9	1	0	0	0
T13	1	0	0	0
T19	6	5	0	0
T25	1	0	0	0
T26	0	2	0	0
T29	1	0	0	0
T49	0	1	0	0
T50	0	20	0	0
T54	0	1	0	0
T58	1	0	0	0
T62	1	0	0	0
T86	0	1	0	0
T90	0	1	0	0
T92	1	0	0	0
T95	0	10	0	0
T96	0	20	0	0
T101	0	20	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48
1	1	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T58,T11,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	5170898	5170418	0	0
selKnown1	5170896	5170416	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	5170898	5170418	0	0
T1	946	945	0	0
T2	1373	1372	0	0
T3	746	745	0	0
T4	586	585	0	0
T5	325	324	0	0
T6	360	359	0	0
T7	361	360	0	0
T19	15359	15358	0	0
T25	692	691	0	0
T31	1019	1018	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	5170896	5170416	0	0
T1	946	945	0	0
T2	1373	1372	0	0
T3	746	745	0	0
T4	586	585	0	0
T5	325	324	0	0
T6	360	359	0	0
T7	361	360	0	0
T19	15359	15358	0	0
T25	692	691	0	0
T31	1019	1018	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T58,T11,T48
1	1	Covered	T58,T11,T48

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T58,T11,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1864	1384	0	0
selKnown1	1754	1274	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1864	1384	0	0
T7	1	0	0	0
T8	2	1	0	0
T9	2	1	0	0
T13	1	0	0	0
T14	0	1	0	0
T19	6	5	0	0
T25	1	0	0	0
T26	0	3	0	0
T29	1	0	0	0
T49	0	1	0	0
T50	0	20	0	0
T57	0	1	0	0
T58	2	1	0	0
T62	1	0	0	0
T92	1	0	0	0
T185	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1754	1274	0	0
T7	1	0	0	0
T8	1	0	0	0
T9	1	0	0	0
T13	1	0	0	0
T19	6	5	0	0
T25	1	0	0	0
T26	0	2	0	0
T29	1	0	0	0
T49	0	1	0	0
T50	0	20	0	0
T54	0	1	0	0
T58	1	0	0	0
T62	1	0	0	0
T86	0	1	0	0
T90	0	1	0	0
T92	1	0	0	0
T95	0	10	0	0
T96	0	20	0	0
T101	0	20	0	0