Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
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Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
86.67 96.15 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_errors_cgs_wrap[rv_dm_mem_reg_block] 92.31 1 100 1 64 64
tl_errors_cgs_wrap[rv_dm_regs_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_errors_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.31 1 100 1 64 64



Summary for Group Instance tl_errors_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 2 13 92.31


Variables for Group Instance tl_errors_cgs_wrap[rv_dm_mem_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 1 1 2
cp_mem_ro_err 2 0 2 100.00 100 1 1 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2


Group Instance : tl_errors_cgs_wrap[rv_dm_regs_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_errors_cgs_wrap[rv_dm_regs_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 3 12 100.00


Variables for Group Instance tl_errors_cgs_wrap[rv_dm_regs_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_csr_size_err 2 0 2 100.00 100 1 1 2
cp_instr_type_err 2 0 2 100.00 100 1 1 2
cp_mem_byte_access_err 2 1 1 50.00 100 0 0 2
cp_mem_ro_err 2 1 1 50.00 100 0 0 2
cp_mem_wo_err 2 1 1 50.00 100 0 0 2
cp_tl_protocol_err 1 0 1 100.00 100 1 1 0
cp_unmapped_err 2 0 2 100.00 100 1 1 2
cp_write_w_instr_type_err 2 0 2 100.00 100 1 1 2


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 44635 1 T41 275 T36 1483 T65 1413
auto[1] 56957 1 T41 435 T36 1312 T65 1629


Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 84730 1 T41 610 T36 2178 T65 2611
auto[1] 16862 1 T41 100 T36 617 T65 431


Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 101592 1 T41 710 T36 2795 T65 3042


Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 101523 1 T41 710 T36 2792 T65 3041
auto[1] 69 1 T36 3 T65 1 T83 5


Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 101592 0 T41 710 T36 2795 T65 3042


Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
covered 16570 1 T41 96 T36 499 T65 627


Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 99390 1 T41 694 T36 2711 T65 2943
auto[1] 2202 1 T41 16 T36 84 T65 99


Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 92755 1 T41 647 T36 2515 T65 2787
auto[1] 8837 1 T41 63 T36 280 T65 255


Summary for Variable cp_csr_size_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_csr_size_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 130974 1 T41 1234 T87 1 T36 3743
auto[1] 981 1 T41 6 T36 21 T65 30


Summary for Variable cp_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_instr_type_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 91442 1 T41 733 T87 1 T36 2564
auto[1] 40513 1 T41 507 T36 1200 T65 1085


Summary for Variable cp_mem_byte_access_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_byte_access_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 131955 0 T41 1240 T87 1 T36 3764


Summary for Variable cp_mem_ro_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_ro_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 131955 0 T41 1240 T87 1 T36 3764


Summary for Variable cp_mem_wo_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_mem_wo_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 131955 0 T41 1240 T87 1 T36 3764


Summary for Variable cp_tl_protocol_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_tl_protocol_err

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
covered 46252 1 T41 236 T36 1219 T65 1387


Summary for Variable cp_unmapped_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_unmapped_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 128753 1 T41 1214 T87 1 T36 3662
auto[1] 3202 1 T41 26 T36 102 T65 72


Summary for Variable cp_write_w_instr_type_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write_w_instr_type_err

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 91039 1 T41 775 T87 1 T36 2542
auto[1] 40916 1 T41 465 T36 1222 T65 1123