Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	293336	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

665120

1

T1

1

T12

1

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	537799	1			T4	1		T17	2		T14	1
values[0x0]	180429	1			T1	1		T2	2		T4	2
values[0x1]	240228	1			T2	1		T13	1		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

762269

1

T1

1

T12

1

T6

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3149	1			T59	1		T41	4		T36	43
valid_sources[0x01]	3968	1			T60	1		T55	1		T41	9
valid_sources[0x02]	4968	1			T41	9		T36	17		T65	48
valid_sources[0x03]	4736	1			T13	2		T60	1		T41	8
valid_sources[0x04]	3339	1			T58	1		T41	6		T36	16
valid_sources[0x05]	4115	1			T41	6		T52	2		T223	1
valid_sources[0x06]	5823	1			T59	2		T41	8		T36	26
valid_sources[0x07]	3237	1			T44	1		T60	1		T41	15
valid_sources[0x08]	3970	1			T41	11		T36	10		T65	32
valid_sources[0x09]	3803	1			T41	11		T36	40		T65	19
valid_sources[0x0a]	3731	1			T41	20		T36	1		T65	14
valid_sources[0x0b]	3402	1			T41	10		T36	2		T65	8
valid_sources[0x0c]	3395	1			T59	1		T41	9		T36	26
valid_sources[0x0d]	3873	1			T41	4		T36	14		T65	29
valid_sources[0x0e]	3747	1			T41	10		T52	1		T36	27
valid_sources[0x0f]	3790	1			T41	11		T65	39		T9	16
valid_sources[0x10]	3781	1			T41	10		T36	8		T65	52
valid_sources[0x11]	3704	1			T41	9		T51	1		T36	12
valid_sources[0x12]	3965	1			T60	1		T41	4		T36	15
valid_sources[0x13]	3539	1			T41	5		T36	17		T65	16
valid_sources[0x14]	3523	1			T59	1		T58	1		T41	2
valid_sources[0x15]	3634	1			T60	1		T41	13		T36	39
valid_sources[0x16]	3862	1			T59	1		T41	11		T36	17
valid_sources[0x17]	3942	1			T41	12		T36	21		T31	1
valid_sources[0x18]	4018	1			T41	8		T36	26		T65	22
valid_sources[0x19]	11244	1			T41	5		T36	17		T65	10
valid_sources[0x1a]	3699	1			T60	2		T41	6		T36	60
valid_sources[0x1b]	3344	1			T41	9		T36	13		T65	30
valid_sources[0x1c]	3180	1			T59	1		T57	1		T41	5
valid_sources[0x1d]	4175	1			T41	6		T51	1		T36	7
valid_sources[0x1e]	3976	1			T59	2		T41	5		T36	17
valid_sources[0x1f]	3734	1			T41	8		T36	15		T65	32
valid_sources[0x20]	3337	1			T59	1		T102	1		T41	12
valid_sources[0x21]	3113	1			T4	1		T41	11		T36	4
valid_sources[0x22]	3468	1			T41	9		T36	148		T65	17
valid_sources[0x23]	4544	1			T41	9		T52	1		T36	31
valid_sources[0x24]	3333	1			T59	1		T60	1		T41	9
valid_sources[0x25]	3626	1			T41	3		T36	11		T65	30
valid_sources[0x26]	3766	1			T60	1		T41	11		T51	1
valid_sources[0x27]	3863	1			T60	1		T41	6		T51	1
valid_sources[0x28]	3516	1			T59	4		T62	1		T41	13
valid_sources[0x29]	4139	1			T59	1		T41	7		T36	8
valid_sources[0x2a]	3640	1			T41	9		T65	21		T9	15
valid_sources[0x2b]	3127	1			T50	2		T41	12		T52	1
valid_sources[0x2c]	3418	1			T60	1		T41	6		T36	8
valid_sources[0x2d]	3620	1			T55	1		T50	1		T41	15
valid_sources[0x2e]	4066	1			T59	1		T41	14		T36	20
valid_sources[0x2f]	3429	1			T41	6		T67	2		T36	1
valid_sources[0x30]	3798	1			T41	17		T36	13		T177	3
valid_sources[0x31]	4146	1			T43	2		T41	14		T36	11
valid_sources[0x32]	4583	1			T17	2		T55	1		T41	10
valid_sources[0x33]	3919	1			T41	12		T36	5		T177	1
valid_sources[0x34]	3383	1			T41	9		T36	31		T65	18
valid_sources[0x35]	3546	1			T41	8		T36	43		T65	17
valid_sources[0x36]	4717	1			T60	1		T41	6		T36	34
valid_sources[0x37]	3716	1			T6	1		T41	8		T36	19
valid_sources[0x38]	4160	1			T59	3		T60	1		T41	11
valid_sources[0x39]	3849	1			T41	7		T51	1		T36	8
valid_sources[0x3a]	4332	1			T62	3		T41	6		T36	219
valid_sources[0x3b]	3786	1			T44	1		T41	13		T36	2
valid_sources[0x3c]	3752	1			T4	2		T59	1		T60	1
valid_sources[0x3d]	3259	1			T44	4		T41	12		T36	25
valid_sources[0x3e]	3576	1			T60	1		T41	5		T36	24
valid_sources[0x3f]	3525	1			T43	1		T41	6		T79	1
valid_sources[0x40]	4003	1			T60	2		T41	7		T36	7
valid_sources[0x41]	3711	1			T59	1		T41	9		T36	3
valid_sources[0x42]	3661	1			T12	1		T59	1		T68	2
valid_sources[0x43]	3246	1			T59	2		T41	6		T36	6
valid_sources[0x44]	3528	1			T41	9		T36	23		T65	26
valid_sources[0x45]	3707	1			T41	7		T36	7		T65	42
valid_sources[0x46]	3210	1			T47	2		T41	5		T36	18
valid_sources[0x47]	3687	1			T41	10		T36	17		T65	8
valid_sources[0x48]	3616	1			T60	3		T41	10		T36	4
valid_sources[0x49]	3830	1			T41	7		T32	1		T36	13
valid_sources[0x4a]	3818	1			T41	5		T79	1		T36	11
valid_sources[0x4b]	3890	1			T41	10		T79	1		T36	60
valid_sources[0x4c]	3543	1			T41	7		T65	17		T9	27
valid_sources[0x4d]	4294	1			T59	1		T62	1		T41	13
valid_sources[0x4e]	3561	1			T60	1		T41	8		T36	14
valid_sources[0x4f]	3328	1			T41	7		T36	8		T65	5
valid_sources[0x50]	3827	1			T41	11		T36	16		T65	2
valid_sources[0x51]	3400	1			T41	6		T36	3		T65	31
valid_sources[0x52]	2969	1			T55	1		T41	17		T36	4
valid_sources[0x53]	4325	1			T41	9		T32	1		T36	12
valid_sources[0x54]	3246	1			T41	12		T79	1		T67	4
valid_sources[0x55]	3889	1			T41	14		T36	27		T65	10
valid_sources[0x56]	2895	1			T41	7		T36	18		T65	12
valid_sources[0x57]	3433	1			T60	1		T41	7		T36	8
valid_sources[0x58]	3435	1			T41	10		T36	3		T65	8
valid_sources[0x59]	3216	1			T41	10		T87	1		T36	7
valid_sources[0x5a]	3464	1			T41	10		T36	20		T65	14
valid_sources[0x5b]	4098	1			T41	8		T36	12		T65	13
valid_sources[0x5c]	4585	1			T92	2		T41	16		T36	22
valid_sources[0x5d]	3587	1			T97	1		T41	12		T33	6
valid_sources[0x5e]	4041	1			T41	10		T36	22		T65	35
valid_sources[0x5f]	4316	1			T41	10		T36	5		T65	13
valid_sources[0x60]	3357	1			T41	17		T36	21		T65	16
valid_sources[0x61]	3205	1			T41	8		T79	1		T36	46
valid_sources[0x62]	3956	1			T45	2		T41	14		T36	8
valid_sources[0x63]	3324	1			T41	8		T65	15		T9	14
valid_sources[0x64]	3942	1			T60	1		T41	5		T67	1
valid_sources[0x65]	3257	1			T50	1		T41	2		T36	19
valid_sources[0x66]	3400	1			T24	3		T60	1		T41	10
valid_sources[0x67]	3831	1			T60	1		T41	15		T65	32
valid_sources[0x68]	3659	1			T59	1		T41	11		T36	5
valid_sources[0x69]	3874	1			T41	7		T178	2		T99	1
valid_sources[0x6a]	4203	1			T59	2		T41	12		T36	4
valid_sources[0x6b]	3608	1			T85	1		T41	10		T36	1
valid_sources[0x6c]	3376	1			T41	4		T36	4		T65	40
valid_sources[0x6d]	3609	1			T59	2		T41	15		T36	23
valid_sources[0x6e]	3536	1			T60	1		T41	7		T36	1
valid_sources[0x6f]	3861	1			T46	1		T41	10		T79	1
valid_sources[0x70]	3101	1			T55	1		T41	6		T36	20
valid_sources[0x71]	3944	1			T60	1		T41	9		T36	136
valid_sources[0x72]	3989	1			T41	12		T36	2		T65	16
valid_sources[0x73]	3513	1			T41	3		T36	7		T177	2
valid_sources[0x74]	3824	1			T41	11		T36	13		T65	9
valid_sources[0x75]	3341	1			T59	3		T41	9		T36	4
valid_sources[0x76]	4137	1			T41	7		T36	3		T65	21
valid_sources[0x77]	3389	1			T41	5		T65	11		T9	25
valid_sources[0x78]	3566	1			T60	1		T41	4		T36	15
valid_sources[0x79]	3890	1			T41	16		T36	32		T65	11
valid_sources[0x7a]	3093	1			T43	1		T41	3		T36	29
valid_sources[0x7b]	3116	1			T53	7		T41	10		T36	18
valid_sources[0x7c]	3366	1			T41	10		T36	33		T65	13
valid_sources[0x7d]	3675	1			T14	2		T60	1		T41	10
valid_sources[0x7e]	3936	1			T41	16		T79	1		T36	3
valid_sources[0x7f]	3543	1			T58	1		T61	2		T41	8
valid_sources[0x80]	3991	1			T55	1		T41	7		T36	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

320201

1

T17

2

T43

3

T54

3

values[0x0]

all_enables

biggest_size

172531

1

T1

1

T12

1

T6

1

values[0x1]

all_enables

biggest_size

172388

1

T6

1

T39

1

T61

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

114413

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33962	1			T41	373		T87	1		T36	868
values[0x0]	43436	1			T3	1		T4	1		T12	1
values[0x1]	45386	1			T1	1		T2	1		T13	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

117346

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	345	1			T102	1		T22	1		T9	18
valid_sources[0x01]	340	1			T65	3		T9	22		T83	10
valid_sources[0x02]	677	1			T12	1		T224	1		T225	2
valid_sources[0x03]	366	1			T9	20		T83	29		T123	16
valid_sources[0x04]	493	1			T177	1		T9	22		T226	1
valid_sources[0x05]	348	1			T47	6		T227	1		T36	1
valid_sources[0x06]	405	1			T97	1		T65	47		T228	1
valid_sources[0x07]	485	1			T88	2		T9	15		T229	6
valid_sources[0x08]	444	1			T9	19		T226	1		T83	30
valid_sources[0x09]	408	1			T82	2		T191	1		T65	13
valid_sources[0x0a]	365	1			T36	28		T230	1		T65	1
valid_sources[0x0b]	482	1			T9	17		T83	24		T123	8
valid_sources[0x0c]	1212	1			T41	1		T65	72		T231	1
valid_sources[0x0d]	405	1			T232	3		T65	36		T9	19
valid_sources[0x0e]	401	1			T42	1		T84	2		T41	1
valid_sources[0x0f]	607	1			T79	2		T36	107		T9	27
valid_sources[0x10]	355	1			T62	1		T233	3		T234	1
valid_sources[0x11]	399	1			T48	1		T169	1		T73	1
valid_sources[0x12]	449	1			T9	13		T235	1		T83	17
valid_sources[0x13]	516	1			T41	20		T224	2		T36	92
valid_sources[0x14]	420	1			T65	28		T9	17		T83	22
valid_sources[0x15]	560	1			T236	1		T237	1		T65	87
valid_sources[0x16]	362	1			T98	1		T60	1		T79	2
valid_sources[0x17]	542	1			T87	10		T238	1		T65	21
valid_sources[0x18]	386	1			T36	4		T65	1		T9	19
valid_sources[0x19]	417	1			T238	1		T178	1		T65	15
valid_sources[0x1a]	462	1			T41	1		T239	1		T240	1
valid_sources[0x1b]	747	1			T4	1		T29	1		T41	159
valid_sources[0x1c]	396	1			T41	1		T36	75		T234	1
valid_sources[0x1d]	455	1			T36	1		T241	1		T65	2
valid_sources[0x1e]	431	1			T188	2		T65	2		T9	19
valid_sources[0x1f]	445	1			T225	3		T9	22		T83	12
valid_sources[0x20]	485	1			T79	1		T22	1		T234	1
valid_sources[0x21]	421	1			T53	1		T9	22		T83	19
valid_sources[0x22]	414	1			T41	1		T36	1		T65	27
valid_sources[0x23]	388	1			T20	1		T206	1		T193	1
valid_sources[0x24]	371	1			T36	3		T65	1		T242	2
valid_sources[0x25]	450	1			T103	1		T170	10		T65	17
valid_sources[0x26]	590	1			T36	2		T65	30		T9	20
valid_sources[0x27]	657	1			T36	38		T37	1		T65	56
valid_sources[0x28]	345	1			T71	3		T234	1		T241	1
valid_sources[0x29]	820	1			T20	1		T41	1		T36	105
valid_sources[0x2a]	664	1			T36	213		T65	41		T9	10
valid_sources[0x2b]	382	1			T65	11		T9	23		T83	25
valid_sources[0x2c]	590	1			T30	2		T36	97		T65	1
valid_sources[0x2d]	415	1			T82	1		T9	11		T203	7
valid_sources[0x2e]	351	1			T65	6		T9	10		T83	17
valid_sources[0x2f]	311	1			T36	10		T177	2		T33	1
valid_sources[0x30]	431	1			T41	1		T238	2		T36	89
valid_sources[0x31]	344	1			T41	1		T9	14		T83	6
valid_sources[0x32]	336	1			T73	1		T243	1		T65	4
valid_sources[0x33]	396	1			T128	1		T238	1		T236	1
valid_sources[0x34]	466	1			T8	1		T36	4		T65	36
valid_sources[0x35]	579	1			T9	6		T83	14		T123	9
valid_sources[0x36]	448	1			T13	1		T69	1		T65	1
valid_sources[0x37]	433	1			T9	10		T83	39		T244	19
valid_sources[0x38]	488	1			T9	23		T83	59		T123	16
valid_sources[0x39]	361	1			T9	16		T245	1		T83	12
valid_sources[0x3a]	471	1			T78	1		T65	1		T9	13
valid_sources[0x3b]	431	1			T38	1		T73	1		T9	19
valid_sources[0x3c]	351	1			T36	3		T9	18		T83	16
valid_sources[0x3d]	578	1			T36	2		T65	34		T9	17
valid_sources[0x3e]	458	1			T17	1		T68	1		T65	5
valid_sources[0x3f]	423	1			T65	4		T9	18		T83	20
valid_sources[0x40]	310	1			T246	3		T9	16		T83	36
valid_sources[0x41]	403	1			T124	1		T31	1		T65	6
valid_sources[0x42]	679	1			T41	205		T128	1		T36	9
valid_sources[0x43]	446	1			T52	1		T230	1		T65	4
valid_sources[0x44]	275	1			T96	1		T61	1		T65	12
valid_sources[0x45]	338	1			T230	1		T9	28		T83	37
valid_sources[0x46]	518	1			T36	79		T65	46		T247	1
valid_sources[0x47]	533	1			T5	1		T238	1		T65	31
valid_sources[0x48]	328	1			T6	1		T65	10		T9	17
valid_sources[0x49]	423	1			T36	1		T9	19		T248	1
valid_sources[0x4a]	485	1			T72	1		T128	5		T67	1
valid_sources[0x4b]	465	1			T65	72		T88	1		T9	18
valid_sources[0x4c]	520	1			T65	2		T9	21		T83	30
valid_sources[0x4d]	508	1			T33	2		T65	28		T9	29
valid_sources[0x4e]	336	1			T9	29		T83	33		T249	1
valid_sources[0x4f]	506	1			T36	50		T65	4		T9	20
valid_sources[0x50]	452	1			T20	1		T41	3		T79	1
valid_sources[0x51]	582	1			T36	5		T65	7		T9	19
valid_sources[0x52]	396	1			T237	1		T65	35		T9	18
valid_sources[0x53]	456	1			T65	6		T250	1		T9	11
valid_sources[0x54]	510	1			T9	17		T83	27		T123	10
valid_sources[0x55]	392	1			T65	1		T9	27		T251	1
valid_sources[0x56]	872	1			T3	1		T237	1		T36	472
valid_sources[0x57]	544	1			T36	1		T252	2		T65	6
valid_sources[0x58]	340	1			T238	1		T36	1		T9	12
valid_sources[0x59]	549	1			T65	73		T16	2		T9	17
valid_sources[0x5a]	677	1			T65	7		T25	1		T9	15
valid_sources[0x5b]	860	1			T36	84		T253	1		T228	1
valid_sources[0x5c]	467	1			T223	1		T36	2		T65	1
valid_sources[0x5d]	635	1			T95	1		T9	13		T83	23
valid_sources[0x5e]	473	1			T86	1		T142	1		T99	8
valid_sources[0x5f]	517	1			T254	1		T65	1		T9	16
valid_sources[0x60]	332	1			T41	8		T182	1		T65	1
valid_sources[0x61]	363	1			T141	3		T239	1		T255	1
valid_sources[0x62]	621	1			T58	1		T36	1		T234	1
valid_sources[0x63]	514	1			T21	9		T65	31		T9	22
valid_sources[0x64]	336	1			T20	1		T80	1		T184	1
valid_sources[0x65]	707	1			T20	1		T182	1		T252	1
valid_sources[0x66]	497	1			T30	1		T252	1		T65	1
valid_sources[0x67]	606	1			T237	1		T36	1		T65	14
valid_sources[0x68]	358	1			T256	1		T230	1		T65	20
valid_sources[0x69]	444	1			T36	46		T65	30		T9	16
valid_sources[0x6a]	399	1			T28	1		T73	1		T257	1
valid_sources[0x6b]	356	1			T105	1		T41	1		T185	1
valid_sources[0x6c]	451	1			T182	1		T9	20		T83	27
valid_sources[0x6d]	798	1			T73	1		T41	1		T65	14
valid_sources[0x6e]	314	1			T65	9		T9	12		T83	15
valid_sources[0x6f]	422	1			T125	1		T36	66		T65	18
valid_sources[0x70]	478	1			T43	1		T65	43		T9	19
valid_sources[0x71]	413	1			T36	3		T65	62		T88	1
valid_sources[0x72]	750	1			T24	1		T22	2		T65	1
valid_sources[0x73]	369	1			T256	1		T36	1		T258	1
valid_sources[0x74]	457	1			T65	1		T88	1		T9	26
valid_sources[0x75]	411	1			T82	1		T88	1		T9	25
valid_sources[0x76]	652	1			T259	1		T36	99		T260	1
valid_sources[0x77]	427	1			T20	1		T44	1		T85	1
valid_sources[0x78]	449	1			T36	121		T65	2		T9	19
valid_sources[0x79]	774	1			T65	40		T9	14		T83	17
valid_sources[0x7a]	466	1			T82	1		T143	1		T238	1
valid_sources[0x7b]	457	1			T65	1		T9	19		T83	22
valid_sources[0x7c]	645	1			T36	239		T65	7		T9	17
valid_sources[0x7d]	432	1			T23	1		T230	1		T9	15
valid_sources[0x7e]	561	1			T261	1		T36	2		T9	10
valid_sources[0x7f]	644	1			T36	173		T65	77		T9	20
valid_sources[0x80]	377	1			T22	4		T262	1		T9	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30009

1

T41

357

T36

817

T65

722

values[0x0]

all_enables

biggest_size

42344

1

T3

1

T4

1

T12

1

values[0x1]

all_enables

biggest_size

42060

1

T1

1

T2

1

T13

1