Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

752561

1

T2

3

T4

3

T13

2

full_word

681184

1

T1

1

T12

1

T6

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	1433443	1			T1	1		T2	3		T4	3
auto[TlIntgErrCmd]	108	1			T87	1		T88	1		T172	6
auto[TlIntgErrData]	101	1			T172	7		T173	5		T215	5
auto[TlIntgErrBoth]	93	1			T172	7		T173	3		T213	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

556971

1

T4

1

T14

1

T43

3

auto[1]

876774

1

T1

1

T2

3

T4

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	234784	1			T4	1		T14	1		T54	5
auto[TlIntgErrNone]	partial	auto[1]	517497	1			T2	3		T4	2		T13	2
auto[TlIntgErrNone]	full_word	auto[0]	322046	1			T43	3		T54	3		T56	6
auto[TlIntgErrNone]	full_word	auto[1]	359116	1			T1	1		T12	1		T6	2
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T172	5		T173	1		T215	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T87	1		T88	1		T172	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T215	1		T209	1		T219	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T215	1		T209	1		T210	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T172	4		T173	2		T215	4
auto[TlIntgErrData]	partial	auto[1]	40	1			T172	3		T173	2		T215	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T173	1		T220	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T217	1		T221	1		T222	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1			T172	2		T173	1		T213	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T172	3		T173	2		T213	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T172	2		T214	1		T220	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T212	2		T218	1		T221	1