Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.04	100.00	97.62	97.60		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	93960544	164270	0	0
late_debug_enable_rd_A	93960544	7931	0	0
late_debug_enable_regwen_rd_A	93960544	7037	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93960544	164270	0	0
T34	0	2981	0	0
T36	0	4143	0	0
T37	0	3293	0	0
T44	60174	0	0	0
T62	0	6234	0	0
T71	0	9511	0	0
T72	10443	0	0	0
T79	0	4200	0	0
T90	349032	1	0	0
T94	0	11405	0	0
T118	0	9522	0	0
T119	3477	0	0	0
T120	51745	0	0	0
T121	60468	0	0	0
T122	48271	0	0	0
T123	104531	0	0	0
T124	29538	0	0	0
T125	242793	0	0	0
T186	0	1	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93960544	7931	0	0
T34	158443	573	0	0
T36	268918	2094	0	0
T79	0	910	0	0
T134	0	7	0	0
T143	0	90	0	0
T158	0	10	0	0
T176	0	29	0	0
T177	0	27	0	0
T187	0	201	0	0
T188	0	89	0	0
T189	232002	0	0	0
T190	472102	0	0	0
T191	1401	0	0	0
T192	1951	0	0	0
T193	1172	0	0	0
T194	948	0	0	0
T195	3203	0	0	0
T196	129168	0	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93960544	7037	0	0
T34	158443	382	0	0
T36	268918	1757	0	0
T79	0	787	0	0
T134	0	6	0	0
T143	0	64	0	0
T158	0	12	0	0
T176	0	52	0	0
T187	0	116	0	0
T188	0	112	0	0
T189	232002	0	0	0
T190	472102	0	0	0
T191	1401	0	0	0
T192	1951	0	0	0
T193	1172	0	0	0
T194	948	0	0	0
T195	3203	0	0	0
T196	129168	0	0	0
T197	0	6	0	0