| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 89.20 | 96.64 | 90.52 | 92.10 | 93.33 | 90.44 | 98.74 | 62.63 |
| T87 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3525402693 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:35:43 AM UTC 24 | 156673047 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1334103136 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:35:43 AM UTC 24 | 261442339 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.817299692 | Oct 15 12:35:42 AM UTC 24 | Oct 15 12:35:44 AM UTC 24 | 125515229 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1671511773 | Oct 15 12:35:42 AM UTC 24 | Oct 15 12:35:45 AM UTC 24 | 147739619 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2663165378 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:35:45 AM UTC 24 | 2227259819 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.3074771012 | Oct 15 12:35:43 AM UTC 24 | Oct 15 12:35:45 AM UTC 24 | 41034932 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3339317547 | Oct 15 12:35:42 AM UTC 24 | Oct 15 12:35:46 AM UTC 24 | 105366149 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1290968424 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:35:46 AM UTC 24 | 969158625 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3270178079 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:35:47 AM UTC 24 | 604191528 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.936321511 | Oct 15 12:35:44 AM UTC 24 | Oct 15 12:35:47 AM UTC 24 | 549928844 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3673622924 | Oct 15 12:35:45 AM UTC 24 | Oct 15 12:35:47 AM UTC 24 | 149043619 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3280825101 | Oct 15 12:35:45 AM UTC 24 | Oct 15 12:35:48 AM UTC 24 | 390404513 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1730091770 | Oct 15 12:35:47 AM UTC 24 | Oct 15 12:35:48 AM UTC 24 | 49997565 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3307801037 | Oct 15 12:35:47 AM UTC 24 | Oct 15 12:35:49 AM UTC 24 | 66064044 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.709105668 | Oct 15 12:35:44 AM UTC 24 | Oct 15 12:35:49 AM UTC 24 | 125817325 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2456528865 | Oct 15 12:35:47 AM UTC 24 | Oct 15 12:35:49 AM UTC 24 | 365947742 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2130636795 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:35:50 AM UTC 24 | 5468646829 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3558206780 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:35:50 AM UTC 24 | 2199567634 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1684657583 | Oct 15 12:35:48 AM UTC 24 | Oct 15 12:35:51 AM UTC 24 | 194139998 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.472560793 | Oct 15 12:35:45 AM UTC 24 | Oct 15 12:35:52 AM UTC 24 | 5127748437 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2669978042 | Oct 15 12:35:48 AM UTC 24 | Oct 15 12:35:52 AM UTC 24 | 139783336 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3769516477 | Oct 15 12:35:48 AM UTC 24 | Oct 15 12:35:52 AM UTC 24 | 202245459 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.990202596 | Oct 15 12:35:44 AM UTC 24 | Oct 15 12:35:52 AM UTC 24 | 1958321364 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2335403716 | Oct 15 12:35:51 AM UTC 24 | Oct 15 12:35:53 AM UTC 24 | 43509882 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3677488552 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:35:53 AM UTC 24 | 9717746419 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1025358145 | Oct 15 12:35:48 AM UTC 24 | Oct 15 12:35:53 AM UTC 24 | 924833839 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1367892282 | Oct 15 12:35:51 AM UTC 24 | Oct 15 12:35:53 AM UTC 24 | 57228775 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3986977431 | Oct 15 12:35:48 AM UTC 24 | Oct 15 12:35:54 AM UTC 24 | 1396828780 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1269480798 | Oct 15 12:35:47 AM UTC 24 | Oct 15 12:35:55 AM UTC 24 | 358228606 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1828610374 | Oct 15 12:35:49 AM UTC 24 | Oct 15 12:35:55 AM UTC 24 | 1283444612 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2907233505 | Oct 15 12:35:52 AM UTC 24 | Oct 15 12:35:55 AM UTC 24 | 152163281 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3027826189 | Oct 15 12:35:49 AM UTC 24 | Oct 15 12:35:55 AM UTC 24 | 2894799618 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.661003020 | Oct 15 12:35:45 AM UTC 24 | Oct 15 12:35:55 AM UTC 24 | 3726829463 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3029467286 | Oct 15 12:35:52 AM UTC 24 | Oct 15 12:35:56 AM UTC 24 | 206920651 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.3990100152 | Oct 15 12:35:50 AM UTC 24 | Oct 15 12:35:56 AM UTC 24 | 302026897 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1771732508 | Oct 15 12:35:54 AM UTC 24 | Oct 15 12:35:57 AM UTC 24 | 184379191 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.187535739 | Oct 15 12:35:54 AM UTC 24 | Oct 15 12:35:57 AM UTC 24 | 605552796 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.619712428 | Oct 15 12:35:53 AM UTC 24 | Oct 15 12:35:58 AM UTC 24 | 134271832 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.638394601 | Oct 15 12:35:57 AM UTC 24 | Oct 15 12:35:59 AM UTC 24 | 65409672 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.3911519169 | Oct 15 12:35:57 AM UTC 24 | Oct 15 12:35:59 AM UTC 24 | 26991571 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2550893967 | Oct 15 12:35:49 AM UTC 24 | Oct 15 12:36:00 AM UTC 24 | 21364308652 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1594370715 | Oct 15 12:35:57 AM UTC 24 | Oct 15 12:36:01 AM UTC 24 | 481361750 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2143418191 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:36:01 AM UTC 24 | 2351055559 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2603681278 | Oct 15 12:35:53 AM UTC 24 | Oct 15 12:36:01 AM UTC 24 | 2175839285 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3685574882 | Oct 15 12:35:58 AM UTC 24 | Oct 15 12:36:02 AM UTC 24 | 99960256 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1426532302 | Oct 15 12:35:46 AM UTC 24 | Oct 15 12:36:02 AM UTC 24 | 5768590922 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.23711695 | Oct 15 12:35:56 AM UTC 24 | Oct 15 12:36:02 AM UTC 24 | 390059016 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2734318916 | Oct 15 12:35:55 AM UTC 24 | Oct 15 12:36:02 AM UTC 24 | 1776686940 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3770946698 | Oct 15 12:36:02 AM UTC 24 | Oct 15 12:36:04 AM UTC 24 | 144225712 ps | ||
| T346 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3718050510 | Oct 15 12:36:01 AM UTC 24 | Oct 15 12:36:05 AM UTC 24 | 242895806 ps | ||
| T347 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3391251735 | Oct 15 12:36:03 AM UTC 24 | Oct 15 12:36:05 AM UTC 24 | 244285177 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2124943458 | Oct 15 12:35:56 AM UTC 24 | Oct 15 12:36:06 AM UTC 24 | 6519143082 ps | ||
| T349 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2756659108 | Oct 15 12:35:54 AM UTC 24 | Oct 15 12:36:06 AM UTC 24 | 7213111255 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2076154236 | Oct 15 12:36:00 AM UTC 24 | Oct 15 12:36:07 AM UTC 24 | 79466885 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2591176529 | Oct 15 12:36:00 AM UTC 24 | Oct 15 12:36:08 AM UTC 24 | 339757981 ps | ||
| T350 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.986666561 | Oct 15 12:36:02 AM UTC 24 | Oct 15 12:36:09 AM UTC 24 | 3966340620 ps | ||
| T351 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.4016668152 | Oct 15 12:36:07 AM UTC 24 | Oct 15 12:36:09 AM UTC 24 | 26043975 ps | ||
| T352 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3729928984 | Oct 15 12:36:07 AM UTC 24 | Oct 15 12:36:09 AM UTC 24 | 90859386 ps | ||
| T353 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.3959440077 | Oct 15 12:36:06 AM UTC 24 | Oct 15 12:36:10 AM UTC 24 | 151319887 ps | ||
| T235 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3150085048 | Oct 15 12:35:56 AM UTC 24 | Oct 15 12:36:12 AM UTC 24 | 763341266 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3643309971 | Oct 15 12:36:08 AM UTC 24 | Oct 15 12:36:12 AM UTC 24 | 66822464 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.2594427308 | Oct 15 12:36:08 AM UTC 24 | Oct 15 12:36:13 AM UTC 24 | 666121242 ps | ||
| T354 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3897158794 | Oct 15 12:36:11 AM UTC 24 | Oct 15 12:36:13 AM UTC 24 | 109562484 ps | ||
| T355 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1331377450 | Oct 15 12:36:10 AM UTC 24 | Oct 15 12:36:13 AM UTC 24 | 113614094 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2592024801 | Oct 15 12:35:47 AM UTC 24 | Oct 15 12:36:14 AM UTC 24 | 8508826419 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3575035079 | Oct 15 12:35:55 AM UTC 24 | Oct 15 12:36:15 AM UTC 24 | 7820711552 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2277563126 | Oct 15 12:36:03 AM UTC 24 | Oct 15 12:36:15 AM UTC 24 | 4444139834 ps | ||
| T356 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3892310590 | Oct 15 12:35:46 AM UTC 24 | Oct 15 12:36:15 AM UTC 24 | 22346195105 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3454784235 | Oct 15 12:36:06 AM UTC 24 | Oct 15 12:36:17 AM UTC 24 | 454000660 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.3679371866 | Oct 15 12:36:14 AM UTC 24 | Oct 15 12:36:18 AM UTC 24 | 61358111 ps | ||
| T357 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2000203061 | Oct 15 12:36:16 AM UTC 24 | Oct 15 12:36:19 AM UTC 24 | 409464969 ps | ||
| T358 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4253265537 | Oct 15 12:35:48 AM UTC 24 | Oct 15 12:36:19 AM UTC 24 | 960790742 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3778192988 | Oct 15 12:36:10 AM UTC 24 | Oct 15 12:36:19 AM UTC 24 | 2075888103 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3760492002 | Oct 15 12:35:48 AM UTC 24 | Oct 15 12:36:21 AM UTC 24 | 1832055726 ps | ||
| T359 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1371064684 | Oct 15 12:36:14 AM UTC 24 | Oct 15 12:36:21 AM UTC 24 | 222909948 ps | ||
| T360 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3538033853 | Oct 15 12:36:11 AM UTC 24 | Oct 15 12:36:22 AM UTC 24 | 3008970214 ps | ||
| T361 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.994305846 | Oct 15 12:36:16 AM UTC 24 | Oct 15 12:36:23 AM UTC 24 | 108614529 ps | ||
| T241 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.799038189 | Oct 15 12:35:51 AM UTC 24 | Oct 15 12:36:24 AM UTC 24 | 1605034507 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.890549715 | Oct 15 12:36:21 AM UTC 24 | Oct 15 12:36:25 AM UTC 24 | 38807176 ps | ||
| T362 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2448624027 | Oct 15 12:36:20 AM UTC 24 | Oct 15 12:36:27 AM UTC 24 | 366452654 ps | ||
| T363 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.638799413 | Oct 15 12:36:22 AM UTC 24 | Oct 15 12:36:26 AM UTC 24 | 379995059 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1193698207 | Oct 15 12:36:52 AM UTC 24 | Oct 15 12:36:55 AM UTC 24 | 1153384105 ps | ||
| T365 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3246313298 | Oct 15 12:35:49 AM UTC 24 | Oct 15 12:36:26 AM UTC 24 | 41373942081 ps | ||
| T366 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1178503529 | Oct 15 12:35:46 AM UTC 24 | Oct 15 12:36:26 AM UTC 24 | 55435516323 ps | ||
| T367 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2778420766 | Oct 15 12:36:23 AM UTC 24 | Oct 15 12:36:27 AM UTC 24 | 2106743850 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3120995853 | Oct 15 12:36:15 AM UTC 24 | Oct 15 12:36:27 AM UTC 24 | 1548066035 ps | ||
| T368 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.998787598 | Oct 15 12:36:22 AM UTC 24 | Oct 15 12:36:28 AM UTC 24 | 157378511 ps | ||
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| T369 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1036942600 | Oct 15 12:36:03 AM UTC 24 | Oct 15 12:36:29 AM UTC 24 | 7388771068 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3390552966 | Oct 15 12:36:22 AM UTC 24 | Oct 15 12:36:29 AM UTC 24 | 1490782848 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4127935359 | Oct 15 12:35:53 AM UTC 24 | Oct 15 12:36:30 AM UTC 24 | 1592981037 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2283006180 | Oct 15 12:36:24 AM UTC 24 | Oct 15 12:36:30 AM UTC 24 | 1606113067 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.943322235 | Oct 15 12:36:29 AM UTC 24 | Oct 15 12:36:31 AM UTC 24 | 521193309 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3765479412 | Oct 15 12:36:25 AM UTC 24 | Oct 15 12:36:31 AM UTC 24 | 313466861 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4115672143 | Oct 15 12:36:27 AM UTC 24 | Oct 15 12:36:32 AM UTC 24 | 142204678 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2226186792 | Oct 15 12:36:29 AM UTC 24 | Oct 15 12:36:32 AM UTC 24 | 1207944295 ps | ||
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| T179 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2703932507 | Oct 15 12:36:27 AM UTC 24 | Oct 15 12:36:33 AM UTC 24 | 562274462 ps | ||
| T374 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1403562233 | Oct 15 12:36:18 AM UTC 24 | Oct 15 12:36:33 AM UTC 24 | 5408573494 ps | ||
| T375 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.756357792 | Oct 15 12:36:32 AM UTC 24 | Oct 15 12:36:35 AM UTC 24 | 288519786 ps | ||
| T376 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.561186731 | Oct 15 12:36:16 AM UTC 24 | Oct 15 12:36:35 AM UTC 24 | 6754056326 ps | ||
| T377 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1870654577 | Oct 15 12:36:30 AM UTC 24 | Oct 15 12:36:35 AM UTC 24 | 436850675 ps | ||
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| T379 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.569393591 | Oct 15 12:36:31 AM UTC 24 | Oct 15 12:36:36 AM UTC 24 | 140656198 ps | ||
| T380 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3609537834 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:36:36 AM UTC 24 | 54850383060 ps | ||
| T381 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1249512373 | Oct 15 12:36:32 AM UTC 24 | Oct 15 12:36:37 AM UTC 24 | 238709744 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.302225238 | Oct 15 12:35:50 AM UTC 24 | Oct 15 12:36:38 AM UTC 24 | 6387619149 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1810204676 | Oct 15 12:36:31 AM UTC 24 | Oct 15 12:36:39 AM UTC 24 | 728387698 ps | ||
| T382 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2563517416 | Oct 15 12:36:36 AM UTC 24 | Oct 15 12:36:39 AM UTC 24 | 104581318 ps | ||
| T245 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1800984866 | Oct 15 12:36:26 AM UTC 24 | Oct 15 12:36:39 AM UTC 24 | 2846801337 ps | ||
| T383 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2750016558 | Oct 15 12:36:30 AM UTC 24 | Oct 15 12:36:39 AM UTC 24 | 2355716647 ps | ||
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| T384 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1451882428 | Oct 15 12:36:33 AM UTC 24 | Oct 15 12:36:41 AM UTC 24 | 2574955870 ps | ||
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| T387 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2355979742 | Oct 15 12:36:34 AM UTC 24 | Oct 15 12:36:42 AM UTC 24 | 116843185 ps | ||
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| T91 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3272206061 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:36:44 AM UTC 24 | 7969137134 ps | ||
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| T181 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1754674895 | Oct 15 12:36:36 AM UTC 24 | Oct 15 12:36:44 AM UTC 24 | 282101673 ps | ||
| T239 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.555988683 | Oct 15 12:36:20 AM UTC 24 | Oct 15 12:36:45 AM UTC 24 | 2338593134 ps | ||
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| T391 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3792989994 | Oct 15 12:36:43 AM UTC 24 | Oct 15 12:36:45 AM UTC 24 | 138489870 ps | ||
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| T394 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3626753259 | Oct 15 12:36:44 AM UTC 24 | Oct 15 12:36:46 AM UTC 24 | 58060794 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3249941230 | Oct 15 12:35:44 AM UTC 24 | Oct 15 12:36:47 AM UTC 24 | 8893523233 ps | ||
| T395 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2991666234 | Oct 15 12:36:13 AM UTC 24 | Oct 15 12:36:47 AM UTC 24 | 7596795074 ps | ||
| T396 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2754616141 | Oct 15 12:36:03 AM UTC 24 | Oct 15 12:36:48 AM UTC 24 | 20660420345 ps | ||
| T397 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2719403152 | Oct 15 12:36:46 AM UTC 24 | Oct 15 12:36:48 AM UTC 24 | 192461391 ps | ||
| T398 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.600757207 | Oct 15 12:36:39 AM UTC 24 | Oct 15 12:36:48 AM UTC 24 | 346460986 ps | ||
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| T402 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.1553820569 | Oct 15 12:36:45 AM UTC 24 | Oct 15 12:36:50 AM UTC 24 | 177831857 ps | ||
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| T406 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.701459324 | Oct 15 12:35:50 AM UTC 24 | Oct 15 12:36:51 AM UTC 24 | 35468456069 ps | ||
| T407 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3855599390 | Oct 15 12:36:10 AM UTC 24 | Oct 15 12:36:51 AM UTC 24 | 2164610934 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2141992469 | Oct 15 12:36:39 AM UTC 24 | Oct 15 12:36:51 AM UTC 24 | 611654212 ps | ||
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| T412 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1090015560 | Oct 15 12:36:42 AM UTC 24 | Oct 15 12:36:52 AM UTC 24 | 1730493284 ps | ||
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| T414 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.648536965 | Oct 15 12:36:49 AM UTC 24 | Oct 15 12:36:54 AM UTC 24 | 85975333 ps | ||
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| T418 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1603587181 | Oct 15 12:35:41 AM UTC 24 | Oct 15 12:36:55 AM UTC 24 | 4559893444 ps | ||
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| T419 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1182936614 | Oct 15 12:36:51 AM UTC 24 | Oct 15 12:36:55 AM UTC 24 | 302711562 ps | ||
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| T424 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.646779131 | Oct 15 12:36:46 AM UTC 24 | Oct 15 12:36:57 AM UTC 24 | 709303029 ps | ||
| T425 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3963587385 | Oct 15 12:36:50 AM UTC 24 | Oct 15 12:36:58 AM UTC 24 | 493514900 ps | ||
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| T428 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3963016821 | Oct 15 12:36:52 AM UTC 24 | Oct 15 12:36:58 AM UTC 24 | 241248821 ps | ||
| T429 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3865787124 | Oct 15 12:36:56 AM UTC 24 | Oct 15 12:36:58 AM UTC 24 | 76747007 ps | ||
| T430 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1697386836 | Oct 15 12:36:52 AM UTC 24 | Oct 15 12:36:59 AM UTC 24 | 647141543 ps | ||
| T431 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.249704762 | Oct 15 12:36:53 AM UTC 24 | Oct 15 12:36:59 AM UTC 24 | 1964037538 ps | ||
| T432 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2361257684 | Oct 15 12:36:47 AM UTC 24 | Oct 15 12:37:00 AM UTC 24 | 2910854399 ps | ||
| T433 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.138862233 | Oct 15 12:36:48 AM UTC 24 | Oct 15 12:37:00 AM UTC 24 | 4170300858 ps | ||
| T434 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1378452664 | Oct 15 12:36:56 AM UTC 24 | Oct 15 12:37:00 AM UTC 24 | 351512629 ps | ||
| T244 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.217217739 | Oct 15 12:36:34 AM UTC 24 | Oct 15 12:37:00 AM UTC 24 | 2971021233 ps | ||
| T435 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1701398650 | Oct 15 12:36:51 AM UTC 24 | Oct 15 12:37:00 AM UTC 24 | 250155922 ps | ||
| T436 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2303312915 | Oct 15 12:36:56 AM UTC 24 | Oct 15 12:37:01 AM UTC 24 | 238116937 ps | ||
| T437 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2309080317 | Oct 15 12:36:53 AM UTC 24 | Oct 15 12:37:01 AM UTC 24 | 2761989936 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.1964788521 | Oct 15 12:36:57 AM UTC 24 | Oct 15 12:37:01 AM UTC 24 | 348326824 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1574852793 | Oct 15 12:36:58 AM UTC 24 | Oct 15 12:37:01 AM UTC 24 | 291975764 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1694630009 | Oct 15 12:36:56 AM UTC 24 | Oct 15 12:37:02 AM UTC 24 | 3419946159 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.944030065 | Oct 15 12:36:56 AM UTC 24 | Oct 15 12:37:02 AM UTC 24 | 5895581823 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.990006743 | Oct 15 12:36:54 AM UTC 24 | Oct 15 12:37:03 AM UTC 24 | 834861190 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4008396507 | Oct 15 12:36:58 AM UTC 24 | Oct 15 12:37:03 AM UTC 24 | 363401948 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.3670579200 | Oct 15 12:36:57 AM UTC 24 | Oct 15 12:37:03 AM UTC 24 | 471609135 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.110835990 | Oct 15 12:36:49 AM UTC 24 | Oct 15 12:37:03 AM UTC 24 | 6800995762 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1105967540 | Oct 15 12:36:13 AM UTC 24 | Oct 15 12:37:04 AM UTC 24 | 2481111551 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3461256236 | Oct 15 12:36:52 AM UTC 24 | Oct 15 12:37:05 AM UTC 24 | 2929356567 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3151153589 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:06 AM UTC 24 | 227371747 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.470458682 | Oct 15 12:35:56 AM UTC 24 | Oct 15 12:37:06 AM UTC 24 | 10130840512 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.818468572 | Oct 15 12:36:50 AM UTC 24 | Oct 15 12:37:07 AM UTC 24 | 2516305332 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3386408494 | Oct 15 12:36:57 AM UTC 24 | Oct 15 12:37:07 AM UTC 24 | 1886233109 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2058090590 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:07 AM UTC 24 | 162722579 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1618787862 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:07 AM UTC 24 | 167768057 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.2250760012 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:07 AM UTC 24 | 130587933 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.2614854443 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:08 AM UTC 24 | 219130009 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2149449203 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:09 AM UTC 24 | 275075653 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1780810202 | Oct 15 12:37:03 AM UTC 24 | Oct 15 12:37:09 AM UTC 24 | 2499162191 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2013797427 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:09 AM UTC 24 | 938492648 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.640254842 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:10 AM UTC 24 | 278407375 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3642136560 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:11 AM UTC 24 | 345806247 ps | ||
| T246 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.519590747 | Oct 15 12:36:45 AM UTC 24 | Oct 15 12:37:11 AM UTC 24 | 1810940431 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3896279111 | Oct 15 12:36:44 AM UTC 24 | Oct 15 12:37:12 AM UTC 24 | 9163996117 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1175365076 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:13 AM UTC 24 | 9022389636 ps | ||
| T236 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.535399975 | Oct 15 12:36:57 AM UTC 24 | Oct 15 12:37:15 AM UTC 24 | 2764408556 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.797391341 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:16 AM UTC 24 | 2011065304 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.393741717 | Oct 15 12:36:54 AM UTC 24 | Oct 15 12:37:17 AM UTC 24 | 6401833667 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2012557336 | Oct 15 12:36:00 AM UTC 24 | Oct 15 12:37:17 AM UTC 24 | 6045641944 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1650938126 | Oct 15 12:36:47 AM UTC 24 | Oct 15 12:37:22 AM UTC 24 | 9795976799 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1616245494 | Oct 15 12:35:47 AM UTC 24 | Oct 15 12:37:24 AM UTC 24 | 22964542231 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2863543884 | Oct 15 12:36:05 AM UTC 24 | Oct 15 12:37:24 AM UTC 24 | 15515082285 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.947605910 | Oct 15 12:36:30 AM UTC 24 | Oct 15 12:37:26 AM UTC 24 | 2553748269 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1597284857 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:29 AM UTC 24 | 1878679702 ps | ||
| T243 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2227105058 | Oct 15 12:37:04 AM UTC 24 | Oct 15 12:37:32 AM UTC 24 | 1653327200 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.539014972 | Oct 15 12:37:03 AM UTC 24 | Oct 15 12:37:37 AM UTC 24 | 26601933413 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3535614437 | Oct 15 12:36:24 AM UTC 24 | Oct 15 12:37:39 AM UTC 24 | 27681047454 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.339059027 | Oct 15 12:36:19 AM UTC 24 | Oct 15 12:37:39 AM UTC 24 | 15361435513 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4153411075 | Oct 15 12:36:34 AM UTC 24 | Oct 15 12:37:56 AM UTC 24 | 3336923994 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4135144273 | Oct 15 12:36:29 AM UTC 24 | Oct 15 12:38:14 AM UTC 24 | 49084127851 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3205709129 | Oct 15 12:36:04 AM UTC 24 | Oct 15 12:38:19 AM UTC 24 | 225601646484 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1035081017 | Oct 15 12:35:56 AM UTC 24 | Oct 15 12:38:24 AM UTC 24 | 45121223954 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.59112776 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 298783641 ps |
| CPU time | 0.93 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59112776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.59112776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2819749502 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3181291052 ps |
| CPU time | 48.28 seconds |
| Started | Oct 15 01:10:39 AM UTC 24 |
| Finished | Oct 15 01:11:39 AM UTC 24 |
| Peak memory | 231920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2819749502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stres s_all_with_rand_reset.2819749502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3591596300 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2129607256 ps |
| CPU time | 2.36 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:57 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591596300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3591596300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1210175528 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 526687756 ps |
| CPU time | 2.56 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:02 AM UTC 24 |
| Peak memory | 256148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210175528 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1210175528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.642997972 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4060481139 ps |
| CPU time | 4.03 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:04 AM UTC 24 |
| Peak memory | 215748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642997972 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.642997972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1916770217 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 7271411123 ps |
| CPU time | 9.88 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:11:04 AM UTC 24 |
| Peak memory | 215876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916770217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1916770217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2637864355 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9455938520 ps |
| CPU time | 24.76 seconds |
| Started | Oct 15 01:11:02 AM UTC 24 |
| Finished | Oct 15 01:11:49 AM UTC 24 |
| Peak memory | 232456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2637864355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stres s_all_with_rand_reset.2637864355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2143418191 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2351055559 ps |
| CPU time | 18.15 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:36:01 AM UTC 24 |
| Peak memory | 225384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143418191 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2143418191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1698021664 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 188629202 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698021664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.1698021664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2816134843 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2396691531 ps |
| CPU time | 7.36 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:07 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816134843 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2816134843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2607259863 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 22807593823 ps |
| CPU time | 86.38 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:12:27 AM UTC 24 |
| Peak memory | 232264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2607259863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stres s_all_with_rand_reset.2607259863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3994006258 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 274744541 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:00 AM UTC 24 |
| Peak memory | 250628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994006258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_buffered_enable.3994006258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1712382388 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 46225664 ps |
| CPU time | 3.79 seconds |
| Started | Oct 15 12:36:36 AM UTC 24 |
| Finished | Oct 15 12:36:41 AM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1712382388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_r and_reset.1712382388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.21908632 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 18452645918 ps |
| CPU time | 16.08 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:47 AM UTC 24 |
| Peak memory | 225900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21908632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.21908632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.567859112 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2383375437 ps |
| CPU time | 35.59 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:12:00 AM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=567859112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress _all_with_rand_reset.567859112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.123195574 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 693029649 ps |
| CPU time | 2.47 seconds |
| Started | Oct 15 01:10:40 AM UTC 24 |
| Finished | Oct 15 01:10:53 AM UTC 24 |
| Peak memory | 214240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123195574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.123195574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.1068131495 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2686846493 ps |
| CPU time | 3.76 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:24 AM UTC 24 |
| Peak memory | 215592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068131495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1068131495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.619712428 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 134271832 ps |
| CPU time | 3.7 seconds |
| Started | Oct 15 12:35:53 AM UTC 24 |
| Finished | Oct 15 12:35:58 AM UTC 24 |
| Peak memory | 231456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=619712428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_ra nd_reset.619712428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2863543884 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 15515082285 ps |
| CPU time | 77.42 seconds |
| Started | Oct 15 12:36:05 AM UTC 24 |
| Finished | Oct 15 12:37:24 AM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2863543884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_re set.2863543884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.2436516784 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3507126896 ps |
| CPU time | 73.42 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:12:08 AM UTC 24 |
| Peak memory | 232696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2436516784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stres s_all_with_rand_reset.2436516784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1492852321 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 4125794589 ps |
| CPU time | 2.03 seconds |
| Started | Oct 15 01:11:02 AM UTC 24 |
| Finished | Oct 15 01:11:19 AM UTC 24 |
| Peak memory | 226088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492852321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1492852321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.37730167 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 129834228 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 01:10:39 AM UTC 24 |
| Finished | Oct 15 01:10:51 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37730167 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.37730167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2456528865 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 365947742 ps |
| CPU time | 1.64 seconds |
| Started | Oct 15 12:35:47 AM UTC 24 |
| Finished | Oct 15 12:35:49 AM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456528865 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2456528865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.476664209 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 519734748 ps |
| CPU time | 1.93 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:53 AM UTC 24 |
| Peak memory | 224280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476664209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.476664209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2119822898 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 16751616395 ps |
| CPU time | 150.21 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:13:31 AM UTC 24 |
| Peak memory | 232704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=2119822898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stres s_all_with_rand_reset.2119822898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.274390158 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3375868041 ps |
| CPU time | 2.38 seconds |
| Started | Oct 15 01:11:34 AM UTC 24 |
| Finished | Oct 15 01:11:39 AM UTC 24 |
| Peak memory | 225736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274390158 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.274390158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3425029598 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 76569606 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 224752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425029598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3425029598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1000520638 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 5334906356 ps |
| CPU time | 8.96 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:55 AM UTC 24 |
| Peak memory | 215540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000520638 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1000520638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3249941230 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 8893523233 ps |
| CPU time | 61.53 seconds |
| Started | Oct 15 12:35:44 AM UTC 24 |
| Finished | Oct 15 12:36:47 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249941230 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.3249941230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2428715139 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3983672610 ps |
| CPU time | 5.39 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:11:00 AM UTC 24 |
| Peak memory | 215564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428715139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.2428715139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.90756656 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 10002133916 ps |
| CPU time | 27.05 seconds |
| Started | Oct 15 01:11:02 AM UTC 24 |
| Finished | Oct 15 01:11:44 AM UTC 24 |
| Peak memory | 225824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90756656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv _dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.90756656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2495551992 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4136834741 ps |
| CPU time | 5.58 seconds |
| Started | Oct 15 01:10:49 AM UTC 24 |
| Finished | Oct 15 01:10:58 AM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495551992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2495551992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2592024801 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 8508826419 ps |
| CPU time | 26.13 seconds |
| Started | Oct 15 12:35:47 AM UTC 24 |
| Finished | Oct 15 12:36:14 AM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592024801 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2592024801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.2812556346 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1547479261 ps |
| CPU time | 2.38 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:48 AM UTC 24 |
| Peak memory | 215232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812556346 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2812556346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.4209167188 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 395922010 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 01:11:02 AM UTC 24 |
| Finished | Oct 15 01:11:17 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209167188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.4209167188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1193841208 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1389126393 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 01:10:44 AM UTC 24 |
| Finished | Oct 15 01:10:47 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193841208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1193841208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2159014742 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1000093061 ps |
| CPU time | 1.79 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:53 AM UTC 24 |
| Peak memory | 214288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159014742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2159014742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2496879580 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3423643194 ps |
| CPU time | 8.76 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:40 AM UTC 24 |
| Peak memory | 215680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496879580 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2496879580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.246582610 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1548208361 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:26 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246582610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.246582610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1334103136 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 261442339 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:43 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334103136 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.1334103136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3948319646 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 26892037748 ps |
| CPU time | 42.76 seconds |
| Started | Oct 15 01:11:00 AM UTC 24 |
| Finished | Oct 15 01:11:44 AM UTC 24 |
| Peak memory | 232444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=3948319646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stres s_all_with_rand_reset.3948319646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3558206780 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2199567634 ps |
| CPU time | 7.47 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:50 AM UTC 24 |
| Peak memory | 215032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558206780 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.3558206780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.990202596 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1958321364 ps |
| CPU time | 7.54 seconds |
| Started | Oct 15 12:35:44 AM UTC 24 |
| Finished | Oct 15 12:35:52 AM UTC 24 |
| Peak memory | 215272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990202596 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.990202596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2959218755 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1372091639 ps |
| CPU time | 3.39 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:34 AM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959218755 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2959218755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.519590747 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1810940431 ps |
| CPU time | 24.07 seconds |
| Started | Oct 15 12:36:45 AM UTC 24 |
| Finished | Oct 15 12:37:11 AM UTC 24 |
| Peak memory | 225284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519590747 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.519590747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.535399975 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2764408556 ps |
| CPU time | 16.45 seconds |
| Started | Oct 15 12:36:57 AM UTC 24 |
| Finished | Oct 15 12:37:15 AM UTC 24 |
| Peak memory | 225404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535399975 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.535399975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2753153097 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 197585996 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:56 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753153097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2753153097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.773939087 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5571258686 ps |
| CPU time | 17.32 seconds |
| Started | Oct 15 01:10:39 AM UTC 24 |
| Finished | Oct 15 01:11:08 AM UTC 24 |
| Peak memory | 215676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773939087 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.773939087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.840030457 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 62715733 ps |
| CPU time | 0.71 seconds |
| Started | Oct 15 01:10:48 AM UTC 24 |
| Finished | Oct 15 01:10:53 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840030457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.840030457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1755433740 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3221466196 ps |
| CPU time | 4.24 seconds |
| Started | Oct 15 01:11:25 AM UTC 24 |
| Finished | Oct 15 01:11:30 AM UTC 24 |
| Peak memory | 215480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755433740 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1755433740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1485083626 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 3118239900 ps |
| CPU time | 4.69 seconds |
| Started | Oct 15 01:11:34 AM UTC 24 |
| Finished | Oct 15 01:11:41 AM UTC 24 |
| Peak memory | 225236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485083626 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1485083626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3093226842 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2312723549 ps |
| CPU time | 7.72 seconds |
| Started | Oct 15 01:11:37 AM UTC 24 |
| Finished | Oct 15 01:11:48 AM UTC 24 |
| Peak memory | 225652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093226842 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3093226842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3577687786 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 177789987 ps |
| CPU time | 3.18 seconds |
| Started | Oct 15 12:36:50 AM UTC 24 |
| Finished | Oct 15 12:36:55 AM UTC 24 |
| Peak memory | 225308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577687786 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3577687786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1088285414 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 109610847 ps |
| CPU time | 1 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 224812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088285414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sparse_lc_gate_fsm.1088285414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3786425985 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 60603226 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 224812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786425985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sparse_lc_gate_fsm.3786425985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1603587181 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4559893444 ps |
| CPU time | 71.8 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:36:55 AM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603587181 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.1603587181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1235488627 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 20487575809 ps |
| CPU time | 65.95 seconds |
| Started | Oct 15 12:35:43 AM UTC 24 |
| Finished | Oct 15 12:36:50 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235488627 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1235488627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3339317547 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 105366149 ps |
| CPU time | 2.64 seconds |
| Started | Oct 15 12:35:42 AM UTC 24 |
| Finished | Oct 15 12:35:46 AM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339317547 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3339317547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.709105668 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 125817325 ps |
| CPU time | 4.17 seconds |
| Started | Oct 15 12:35:44 AM UTC 24 |
| Finished | Oct 15 12:35:49 AM UTC 24 |
| Peak memory | 231496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=709105668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_ra nd_reset.709105668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.3074771012 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 41034932 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 12:35:43 AM UTC 24 |
| Finished | Oct 15 12:35:45 AM UTC 24 |
| Peak memory | 224652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074771012 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3074771012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3609537834 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 54850383060 ps |
| CPU time | 53.65 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:36:36 AM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609537834 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.3609537834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3677488552 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 9717746419 ps |
| CPU time | 10.81 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:53 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677488552 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.3677488552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2663165378 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 2227259819 ps |
| CPU time | 3.19 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:45 AM UTC 24 |
| Peak memory | 214968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663165378 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2663165378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2130636795 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 5468646829 ps |
| CPU time | 7.54 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:50 AM UTC 24 |
| Peak memory | 214964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130636795 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.2130636795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3525402693 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 156673047 ps |
| CPU time | 1.41 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:43 AM UTC 24 |
| Peak memory | 214068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525402693 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.3525402693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1290968424 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 969158625 ps |
| CPU time | 4.34 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:46 AM UTC 24 |
| Peak memory | 214860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290968424 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1290968424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.817299692 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 125515229 ps |
| CPU time | 1.03 seconds |
| Started | Oct 15 12:35:42 AM UTC 24 |
| Finished | Oct 15 12:35:44 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817299692 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.817299692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1671511773 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 147739619 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 12:35:42 AM UTC 24 |
| Finished | Oct 15 12:35:45 AM UTC 24 |
| Peak memory | 214580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671511773 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1671511773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3272206061 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 7969137134 ps |
| CPU time | 61 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:36:44 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3272206061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_re set.3272206061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3270178079 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 604191528 ps |
| CPU time | 4.14 seconds |
| Started | Oct 15 12:35:41 AM UTC 24 |
| Finished | Oct 15 12:35:47 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270178079 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3270178079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4253265537 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 960790742 ps |
| CPU time | 29.93 seconds |
| Started | Oct 15 12:35:48 AM UTC 24 |
| Finished | Oct 15 12:36:19 AM UTC 24 |
| Peak memory | 214992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253265537 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4253265537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2669978042 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 139783336 ps |
| CPU time | 2.56 seconds |
| Started | Oct 15 12:35:48 AM UTC 24 |
| Finished | Oct 15 12:35:52 AM UTC 24 |
| Peak memory | 227572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2669978042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_r and_reset.2669978042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3769516477 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 202245459 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 12:35:48 AM UTC 24 |
| Finished | Oct 15 12:35:52 AM UTC 24 |
| Peak memory | 225332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769516477 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3769516477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1178503529 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 55435516323 ps |
| CPU time | 38.73 seconds |
| Started | Oct 15 12:35:46 AM UTC 24 |
| Finished | Oct 15 12:36:26 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178503529 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.1178503529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3892310590 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 22346195105 ps |
| CPU time | 27.84 seconds |
| Started | Oct 15 12:35:46 AM UTC 24 |
| Finished | Oct 15 12:36:15 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892310590 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.3892310590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.661003020 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3726829463 ps |
| CPU time | 9.1 seconds |
| Started | Oct 15 12:35:45 AM UTC 24 |
| Finished | Oct 15 12:35:55 AM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661003020 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.661003020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1426532302 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5768590922 ps |
| CPU time | 14.46 seconds |
| Started | Oct 15 12:35:46 AM UTC 24 |
| Finished | Oct 15 12:36:02 AM UTC 24 |
| Peak memory | 215212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426532302 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1426532302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3280825101 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 390404513 ps |
| CPU time | 1.98 seconds |
| Started | Oct 15 12:35:45 AM UTC 24 |
| Finished | Oct 15 12:35:48 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280825101 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.3280825101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.472560793 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5127748437 ps |
| CPU time | 5.47 seconds |
| Started | Oct 15 12:35:45 AM UTC 24 |
| Finished | Oct 15 12:35:52 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472560793 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.472560793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.936321511 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 549928844 ps |
| CPU time | 1.9 seconds |
| Started | Oct 15 12:35:44 AM UTC 24 |
| Finished | Oct 15 12:35:47 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936321511 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.936321511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3673622924 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 149043619 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 12:35:45 AM UTC 24 |
| Finished | Oct 15 12:35:47 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673622924 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3673622924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3307801037 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 66064044 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 12:35:47 AM UTC 24 |
| Finished | Oct 15 12:35:49 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307801037 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.3307801037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1730091770 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 49997565 ps |
| CPU time | 0.76 seconds |
| Started | Oct 15 12:35:47 AM UTC 24 |
| Finished | Oct 15 12:35:48 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730091770 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1730091770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3986977431 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1396828780 ps |
| CPU time | 4.94 seconds |
| Started | Oct 15 12:35:48 AM UTC 24 |
| Finished | Oct 15 12:35:54 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986977431 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.3986977431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1616245494 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 22964542231 ps |
| CPU time | 95.5 seconds |
| Started | Oct 15 12:35:47 AM UTC 24 |
| Finished | Oct 15 12:37:24 AM UTC 24 |
| Peak memory | 225660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1616245494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_re set.1616245494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1269480798 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 358228606 ps |
| CPU time | 7.28 seconds |
| Started | Oct 15 12:35:47 AM UTC 24 |
| Finished | Oct 15 12:35:55 AM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269480798 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1269480798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.523985409 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 84875288 ps |
| CPU time | 2.34 seconds |
| Started | Oct 15 12:36:40 AM UTC 24 |
| Finished | Oct 15 12:36:43 AM UTC 24 |
| Peak memory | 227636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=523985409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_r and_reset.523985409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3350887711 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 301269966 ps |
| CPU time | 3.43 seconds |
| Started | Oct 15 12:36:39 AM UTC 24 |
| Finished | Oct 15 12:36:44 AM UTC 24 |
| Peak memory | 225276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350887711 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3350887711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3014026283 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 50853280 ps |
| CPU time | 1.34 seconds |
| Started | Oct 15 12:36:39 AM UTC 24 |
| Finished | Oct 15 12:36:42 AM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014026283 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.3014026283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1670011276 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2734168317 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 12:36:39 AM UTC 24 |
| Finished | Oct 15 12:36:45 AM UTC 24 |
| Peak memory | 214936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670011276 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.1670011276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1317751206 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 305806859 ps |
| CPU time | 1.44 seconds |
| Started | Oct 15 12:36:39 AM UTC 24 |
| Finished | Oct 15 12:36:42 AM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317751206 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1317751206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3356402787 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2351401355 ps |
| CPU time | 8.72 seconds |
| Started | Oct 15 12:36:39 AM UTC 24 |
| Finished | Oct 15 12:36:49 AM UTC 24 |
| Peak memory | 215152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356402787 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.3356402787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.600757207 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 346460986 ps |
| CPU time | 7.44 seconds |
| Started | Oct 15 12:36:39 AM UTC 24 |
| Finished | Oct 15 12:36:48 AM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600757207 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.600757207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2141992469 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 611654212 ps |
| CPU time | 10.65 seconds |
| Started | Oct 15 12:36:39 AM UTC 24 |
| Finished | Oct 15 12:36:51 AM UTC 24 |
| Peak memory | 225596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141992469 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2141992469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1862394573 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 462655659 ps |
| CPU time | 4.38 seconds |
| Started | Oct 15 12:36:43 AM UTC 24 |
| Finished | Oct 15 12:36:48 AM UTC 24 |
| Peak memory | 229512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1862394573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_ rand_reset.1862394573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.2251718961 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 256014395 ps |
| CPU time | 2.15 seconds |
| Started | Oct 15 12:36:42 AM UTC 24 |
| Finished | Oct 15 12:36:45 AM UTC 24 |
| Peak memory | 225192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251718961 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2251718961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2196211668 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5770053282 ps |
| CPU time | 7.67 seconds |
| Started | Oct 15 12:36:41 AM UTC 24 |
| Finished | Oct 15 12:36:50 AM UTC 24 |
| Peak memory | 215220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196211668 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.2196211668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3958591184 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1691716871 ps |
| CPU time | 3.93 seconds |
| Started | Oct 15 12:36:41 AM UTC 24 |
| Finished | Oct 15 12:36:46 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958591184 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.3958591184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2521806764 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 425095465 ps |
| CPU time | 1.88 seconds |
| Started | Oct 15 12:36:40 AM UTC 24 |
| Finished | Oct 15 12:36:43 AM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521806764 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.2521806764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.719209570 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1681654687 ps |
| CPU time | 8.81 seconds |
| Started | Oct 15 12:36:43 AM UTC 24 |
| Finished | Oct 15 12:36:53 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719209570 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.719209570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.3850853903 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1003241885 ps |
| CPU time | 6.21 seconds |
| Started | Oct 15 12:36:42 AM UTC 24 |
| Finished | Oct 15 12:36:49 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850853903 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3850853903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1090015560 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1730493284 ps |
| CPU time | 8.74 seconds |
| Started | Oct 15 12:36:42 AM UTC 24 |
| Finished | Oct 15 12:36:52 AM UTC 24 |
| Peak memory | 225376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090015560 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1090015560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2308825503 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 257169769 ps |
| CPU time | 3.43 seconds |
| Started | Oct 15 12:36:46 AM UTC 24 |
| Finished | Oct 15 12:36:50 AM UTC 24 |
| Peak memory | 229380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2308825503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_ rand_reset.2308825503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.422069205 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 221786874 ps |
| CPU time | 2.18 seconds |
| Started | Oct 15 12:36:45 AM UTC 24 |
| Finished | Oct 15 12:36:49 AM UTC 24 |
| Peak memory | 225236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422069205 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.422069205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3626753259 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 58060794 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 12:36:44 AM UTC 24 |
| Finished | Oct 15 12:36:46 AM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626753259 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.3626753259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3896279111 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 9163996117 ps |
| CPU time | 26.96 seconds |
| Started | Oct 15 12:36:44 AM UTC 24 |
| Finished | Oct 15 12:37:12 AM UTC 24 |
| Peak memory | 215128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896279111 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.3896279111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3792989994 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 138489870 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 12:36:43 AM UTC 24 |
| Finished | Oct 15 12:36:45 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792989994 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.3792989994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.646779131 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 709303029 ps |
| CPU time | 10.31 seconds |
| Started | Oct 15 12:36:46 AM UTC 24 |
| Finished | Oct 15 12:36:57 AM UTC 24 |
| Peak memory | 215156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646779131 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.646779131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.1553820569 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 177831857 ps |
| CPU time | 2.97 seconds |
| Started | Oct 15 12:36:45 AM UTC 24 |
| Finished | Oct 15 12:36:50 AM UTC 24 |
| Peak memory | 225564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553820569 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1553820569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.648536965 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 85975333 ps |
| CPU time | 3.55 seconds |
| Started | Oct 15 12:36:49 AM UTC 24 |
| Finished | Oct 15 12:36:54 AM UTC 24 |
| Peak memory | 231764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=648536965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_r and_reset.648536965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.1105439499 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 181866238 ps |
| CPU time | 2.29 seconds |
| Started | Oct 15 12:36:48 AM UTC 24 |
| Finished | Oct 15 12:36:51 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105439499 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1105439499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2155461478 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3733303419 ps |
| CPU time | 4.69 seconds |
| Started | Oct 15 12:36:47 AM UTC 24 |
| Finished | Oct 15 12:36:53 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155461478 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.2155461478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1650938126 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 9795976799 ps |
| CPU time | 34.03 seconds |
| Started | Oct 15 12:36:47 AM UTC 24 |
| Finished | Oct 15 12:37:22 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650938126 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.1650938126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2719403152 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 192461391 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 12:36:46 AM UTC 24 |
| Finished | Oct 15 12:36:48 AM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719403152 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.2719403152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.138862233 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4170300858 ps |
| CPU time | 10.93 seconds |
| Started | Oct 15 12:36:48 AM UTC 24 |
| Finished | Oct 15 12:37:00 AM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138862233 -assert nopostproc +UV M_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.138862233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.1932961452 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 111600089 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 12:36:47 AM UTC 24 |
| Finished | Oct 15 12:36:51 AM UTC 24 |
| Peak memory | 225392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932961452 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1932961452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2361257684 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2910854399 ps |
| CPU time | 11.93 seconds |
| Started | Oct 15 12:36:47 AM UTC 24 |
| Finished | Oct 15 12:37:00 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361257684 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2361257684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1182936614 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 302711562 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 12:36:51 AM UTC 24 |
| Finished | Oct 15 12:36:55 AM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1182936614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_ rand_reset.1182936614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.110835990 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 6800995762 ps |
| CPU time | 13.05 seconds |
| Started | Oct 15 12:36:49 AM UTC 24 |
| Finished | Oct 15 12:37:03 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110835990 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.110835990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3821688867 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1329935505 ps |
| CPU time | 4.09 seconds |
| Started | Oct 15 12:36:49 AM UTC 24 |
| Finished | Oct 15 12:36:54 AM UTC 24 |
| Peak memory | 214996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821688867 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.3821688867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2609287756 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 132996477 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 12:36:49 AM UTC 24 |
| Finished | Oct 15 12:36:51 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609287756 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.2609287756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1701398650 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 250155922 ps |
| CPU time | 8.77 seconds |
| Started | Oct 15 12:36:51 AM UTC 24 |
| Finished | Oct 15 12:37:00 AM UTC 24 |
| Peak memory | 215360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701398650 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.1701398650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.3963587385 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 493514900 ps |
| CPU time | 6.18 seconds |
| Started | Oct 15 12:36:50 AM UTC 24 |
| Finished | Oct 15 12:36:58 AM UTC 24 |
| Peak memory | 225584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963587385 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3963587385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.818468572 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2516305332 ps |
| CPU time | 15.2 seconds |
| Started | Oct 15 12:36:50 AM UTC 24 |
| Finished | Oct 15 12:37:07 AM UTC 24 |
| Peak memory | 227684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818468572 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.818468572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2927100382 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 221380935 ps |
| CPU time | 4.6 seconds |
| Started | Oct 15 12:36:52 AM UTC 24 |
| Finished | Oct 15 12:36:58 AM UTC 24 |
| Peak memory | 229452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2927100382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_ rand_reset.2927100382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3013292640 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 78767656 ps |
| CPU time | 2.45 seconds |
| Started | Oct 15 12:36:52 AM UTC 24 |
| Finished | Oct 15 12:36:55 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013292640 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3013292640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3441550101 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 152238609 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 12:36:52 AM UTC 24 |
| Finished | Oct 15 12:36:54 AM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441550101 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.3441550101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1193698207 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1153384105 ps |
| CPU time | 2.67 seconds |
| Started | Oct 15 12:36:52 AM UTC 24 |
| Finished | Oct 15 12:36:55 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193698207 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.1193698207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1250332822 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 273348598 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 12:36:52 AM UTC 24 |
| Finished | Oct 15 12:36:54 AM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250332822 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.1250332822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1697386836 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 647141543 ps |
| CPU time | 5.65 seconds |
| Started | Oct 15 12:36:52 AM UTC 24 |
| Finished | Oct 15 12:36:59 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697386836 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.1697386836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.3963016821 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 241248821 ps |
| CPU time | 5.39 seconds |
| Started | Oct 15 12:36:52 AM UTC 24 |
| Finished | Oct 15 12:36:58 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963016821 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3963016821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3461256236 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2929356567 ps |
| CPU time | 11.81 seconds |
| Started | Oct 15 12:36:52 AM UTC 24 |
| Finished | Oct 15 12:37:05 AM UTC 24 |
| Peak memory | 225448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461256236 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3461256236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1378452664 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 351512629 ps |
| CPU time | 3.45 seconds |
| Started | Oct 15 12:36:56 AM UTC 24 |
| Finished | Oct 15 12:37:00 AM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1378452664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_ rand_reset.1378452664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3865787124 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 76747007 ps |
| CPU time | 1.84 seconds |
| Started | Oct 15 12:36:56 AM UTC 24 |
| Finished | Oct 15 12:36:58 AM UTC 24 |
| Peak memory | 224544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865787124 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3865787124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.249704762 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1964037538 ps |
| CPU time | 4.47 seconds |
| Started | Oct 15 12:36:53 AM UTC 24 |
| Finished | Oct 15 12:36:59 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249704762 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.249704762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2309080317 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2761989936 ps |
| CPU time | 6.7 seconds |
| Started | Oct 15 12:36:53 AM UTC 24 |
| Finished | Oct 15 12:37:01 AM UTC 24 |
| Peak memory | 214928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309080317 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.2309080317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4248964141 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 215119873 ps |
| CPU time | 1.62 seconds |
| Started | Oct 15 12:36:53 AM UTC 24 |
| Finished | Oct 15 12:36:56 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248964141 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.4248964141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2303312915 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 238116937 ps |
| CPU time | 4.01 seconds |
| Started | Oct 15 12:36:56 AM UTC 24 |
| Finished | Oct 15 12:37:01 AM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303312915 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.2303312915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.990006743 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 834861190 ps |
| CPU time | 7.3 seconds |
| Started | Oct 15 12:36:54 AM UTC 24 |
| Finished | Oct 15 12:37:03 AM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990006743 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.990006743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.393741717 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 6401833667 ps |
| CPU time | 20.89 seconds |
| Started | Oct 15 12:36:54 AM UTC 24 |
| Finished | Oct 15 12:37:17 AM UTC 24 |
| Peak memory | 232204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393741717 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.393741717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4008396507 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 363401948 ps |
| CPU time | 3.71 seconds |
| Started | Oct 15 12:36:58 AM UTC 24 |
| Finished | Oct 15 12:37:03 AM UTC 24 |
| Peak memory | 232060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=4008396507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_ rand_reset.4008396507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.1964788521 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 348326824 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 12:36:57 AM UTC 24 |
| Finished | Oct 15 12:37:01 AM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964788521 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1964788521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1694630009 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3419946159 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 12:36:56 AM UTC 24 |
| Finished | Oct 15 12:37:02 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694630009 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.1694630009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.944030065 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5895581823 ps |
| CPU time | 5.19 seconds |
| Started | Oct 15 12:36:56 AM UTC 24 |
| Finished | Oct 15 12:37:02 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944030065 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.944030065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2129224989 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 173911967 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 12:36:56 AM UTC 24 |
| Finished | Oct 15 12:36:58 AM UTC 24 |
| Peak memory | 214652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129224989 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.2129224989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3386408494 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1886233109 ps |
| CPU time | 8.46 seconds |
| Started | Oct 15 12:36:57 AM UTC 24 |
| Finished | Oct 15 12:37:07 AM UTC 24 |
| Peak memory | 215148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386408494 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.3386408494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.3670579200 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 471609135 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 12:36:57 AM UTC 24 |
| Finished | Oct 15 12:37:03 AM UTC 24 |
| Peak memory | 225312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670579200 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3670579200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2058090590 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 162722579 ps |
| CPU time | 2.32 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:07 AM UTC 24 |
| Peak memory | 227596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2058090590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_ rand_reset.2058090590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.2614854443 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 219130009 ps |
| CPU time | 3.12 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:08 AM UTC 24 |
| Peak memory | 225292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614854443 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2614854443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.539014972 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 26601933413 ps |
| CPU time | 31.95 seconds |
| Started | Oct 15 12:37:03 AM UTC 24 |
| Finished | Oct 15 12:37:37 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539014972 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.539014972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1780810202 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2499162191 ps |
| CPU time | 4.81 seconds |
| Started | Oct 15 12:37:03 AM UTC 24 |
| Finished | Oct 15 12:37:09 AM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780810202 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.1780810202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1574852793 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 291975764 ps |
| CPU time | 1.98 seconds |
| Started | Oct 15 12:36:58 AM UTC 24 |
| Finished | Oct 15 12:37:01 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574852793 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.1574852793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2013797427 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 938492648 ps |
| CPU time | 4.68 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:09 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013797427 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.2013797427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.640254842 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 278407375 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:10 AM UTC 24 |
| Peak memory | 225356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640254842 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.640254842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1597284857 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 1878679702 ps |
| CPU time | 23.76 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:29 AM UTC 24 |
| Peak memory | 225264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597284857 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1597284857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1618787862 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 167768057 ps |
| CPU time | 1.97 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:07 AM UTC 24 |
| Peak memory | 226548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1618787862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_ rand_reset.1618787862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.2250760012 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 130587933 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:07 AM UTC 24 |
| Peak memory | 225192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250760012 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2250760012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.797391341 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2011065304 ps |
| CPU time | 10.83 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:16 AM UTC 24 |
| Peak memory | 214880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797391341 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.797391341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1175365076 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 9022389636 ps |
| CPU time | 7.6 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:13 AM UTC 24 |
| Peak memory | 214936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175365076 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.1175365076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3151153589 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 227371747 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:06 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151153589 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.3151153589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2149449203 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 275075653 ps |
| CPU time | 4.06 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:09 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149449203 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.2149449203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3642136560 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 345806247 ps |
| CPU time | 5.76 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:11 AM UTC 24 |
| Peak memory | 225504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642136560 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3642136560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2227105058 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1653327200 ps |
| CPU time | 26.58 seconds |
| Started | Oct 15 12:37:04 AM UTC 24 |
| Finished | Oct 15 12:37:32 AM UTC 24 |
| Peak memory | 225344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227105058 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2227105058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3760492002 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1832055726 ps |
| CPU time | 31.25 seconds |
| Started | Oct 15 12:35:48 AM UTC 24 |
| Finished | Oct 15 12:36:21 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760492002 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.3760492002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1302172253 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 12733611865 ps |
| CPU time | 39.43 seconds |
| Started | Oct 15 12:35:52 AM UTC 24 |
| Finished | Oct 15 12:36:33 AM UTC 24 |
| Peak memory | 215100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302172253 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1302172253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3029467286 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 206920651 ps |
| CPU time | 2.82 seconds |
| Started | Oct 15 12:35:52 AM UTC 24 |
| Finished | Oct 15 12:35:56 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029467286 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3029467286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2907233505 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 152163281 ps |
| CPU time | 2.23 seconds |
| Started | Oct 15 12:35:52 AM UTC 24 |
| Finished | Oct 15 12:35:55 AM UTC 24 |
| Peak memory | 225188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907233505 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2907233505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2357088340 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 62638696386 ps |
| CPU time | 63.91 seconds |
| Started | Oct 15 12:35:50 AM UTC 24 |
| Finished | Oct 15 12:36:55 AM UTC 24 |
| Peak memory | 215196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357088340 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.2357088340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.701459324 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 35468456069 ps |
| CPU time | 59.73 seconds |
| Started | Oct 15 12:35:50 AM UTC 24 |
| Finished | Oct 15 12:36:51 AM UTC 24 |
| Peak memory | 215216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701459324 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.701459324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2550893967 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 21364308652 ps |
| CPU time | 9.29 seconds |
| Started | Oct 15 12:35:49 AM UTC 24 |
| Finished | Oct 15 12:36:00 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550893967 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.2550893967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3027826189 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2894799618 ps |
| CPU time | 4.74 seconds |
| Started | Oct 15 12:35:49 AM UTC 24 |
| Finished | Oct 15 12:35:55 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027826189 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3027826189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1828610374 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1283444612 ps |
| CPU time | 4.79 seconds |
| Started | Oct 15 12:35:49 AM UTC 24 |
| Finished | Oct 15 12:35:55 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828610374 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.1828610374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3246313298 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 41373942081 ps |
| CPU time | 35.27 seconds |
| Started | Oct 15 12:35:49 AM UTC 24 |
| Finished | Oct 15 12:36:26 AM UTC 24 |
| Peak memory | 215156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246313298 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.3246313298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1684657583 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 194139998 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 12:35:48 AM UTC 24 |
| Finished | Oct 15 12:35:51 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684657583 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.1684657583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1025358145 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 924833839 ps |
| CPU time | 3.88 seconds |
| Started | Oct 15 12:35:48 AM UTC 24 |
| Finished | Oct 15 12:35:53 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025358145 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1025358145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1367892282 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 57228775 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 12:35:51 AM UTC 24 |
| Finished | Oct 15 12:35:53 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367892282 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.1367892282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.2335403716 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 43509882 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 12:35:51 AM UTC 24 |
| Finished | Oct 15 12:35:53 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335403716 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2335403716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2603681278 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2175839285 ps |
| CPU time | 7.08 seconds |
| Started | Oct 15 12:35:53 AM UTC 24 |
| Finished | Oct 15 12:36:01 AM UTC 24 |
| Peak memory | 215168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603681278 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.2603681278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.302225238 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 6387619149 ps |
| CPU time | 46.98 seconds |
| Started | Oct 15 12:35:50 AM UTC 24 |
| Finished | Oct 15 12:36:38 AM UTC 24 |
| Peak memory | 232060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=302225238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.302225238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.3990100152 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 302026897 ps |
| CPU time | 5.34 seconds |
| Started | Oct 15 12:35:50 AM UTC 24 |
| Finished | Oct 15 12:35:56 AM UTC 24 |
| Peak memory | 225400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990100152 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3990100152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.799038189 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1605034507 ps |
| CPU time | 31.4 seconds |
| Started | Oct 15 12:35:51 AM UTC 24 |
| Finished | Oct 15 12:36:24 AM UTC 24 |
| Peak memory | 225316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799038189 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.799038189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4127935359 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1592981037 ps |
| CPU time | 35.58 seconds |
| Started | Oct 15 12:35:53 AM UTC 24 |
| Finished | Oct 15 12:36:30 AM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127935359 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.4127935359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4039015844 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 20330260392 ps |
| CPU time | 34.89 seconds |
| Started | Oct 15 12:35:59 AM UTC 24 |
| Finished | Oct 15 12:36:35 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039015844 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.4039015844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1594370715 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 481361750 ps |
| CPU time | 2.6 seconds |
| Started | Oct 15 12:35:57 AM UTC 24 |
| Finished | Oct 15 12:36:01 AM UTC 24 |
| Peak memory | 225384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594370715 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1594370715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2076154236 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 79466885 ps |
| CPU time | 5.55 seconds |
| Started | Oct 15 12:36:00 AM UTC 24 |
| Finished | Oct 15 12:36:07 AM UTC 24 |
| Peak memory | 231812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=2076154236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_r and_reset.2076154236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.3685574882 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 99960256 ps |
| CPU time | 2.54 seconds |
| Started | Oct 15 12:35:58 AM UTC 24 |
| Finished | Oct 15 12:36:02 AM UTC 24 |
| Peak memory | 225256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685574882 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3685574882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1035081017 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 45121223954 ps |
| CPU time | 145.76 seconds |
| Started | Oct 15 12:35:56 AM UTC 24 |
| Finished | Oct 15 12:38:24 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035081017 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.1035081017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2124943458 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 6519143082 ps |
| CPU time | 9.18 seconds |
| Started | Oct 15 12:35:56 AM UTC 24 |
| Finished | Oct 15 12:36:06 AM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124943458 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.2124943458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3575035079 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 7820711552 ps |
| CPU time | 19.19 seconds |
| Started | Oct 15 12:35:55 AM UTC 24 |
| Finished | Oct 15 12:36:15 AM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575035079 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.3575035079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2131678207 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 13118042019 ps |
| CPU time | 48.69 seconds |
| Started | Oct 15 12:35:56 AM UTC 24 |
| Finished | Oct 15 12:36:46 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131678207 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2131678207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2734318916 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1776686940 ps |
| CPU time | 6.89 seconds |
| Started | Oct 15 12:35:55 AM UTC 24 |
| Finished | Oct 15 12:36:02 AM UTC 24 |
| Peak memory | 214792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734318916 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.2734318916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2756659108 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 7213111255 ps |
| CPU time | 10.51 seconds |
| Started | Oct 15 12:35:54 AM UTC 24 |
| Finished | Oct 15 12:36:06 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756659108 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.2756659108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.187535739 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 605552796 ps |
| CPU time | 1.39 seconds |
| Started | Oct 15 12:35:54 AM UTC 24 |
| Finished | Oct 15 12:35:57 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187535739 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.187535739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1771732508 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 184379191 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 12:35:54 AM UTC 24 |
| Finished | Oct 15 12:35:57 AM UTC 24 |
| Peak memory | 214592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771732508 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1771732508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.638394601 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 65409672 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 12:35:57 AM UTC 24 |
| Finished | Oct 15 12:35:59 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638394601 -assert nopostproc +UVM_ TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.638394601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.3911519169 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 26991571 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 12:35:57 AM UTC 24 |
| Finished | Oct 15 12:35:59 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911519169 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3911519169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2591176529 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 339757981 ps |
| CPU time | 6.31 seconds |
| Started | Oct 15 12:36:00 AM UTC 24 |
| Finished | Oct 15 12:36:08 AM UTC 24 |
| Peak memory | 215120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591176529 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.2591176529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.470458682 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 10130840512 ps |
| CPU time | 68.64 seconds |
| Started | Oct 15 12:35:56 AM UTC 24 |
| Finished | Oct 15 12:37:06 AM UTC 24 |
| Peak memory | 229716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=470458682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.470458682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.23711695 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 390059016 ps |
| CPU time | 4.97 seconds |
| Started | Oct 15 12:35:56 AM UTC 24 |
| Finished | Oct 15 12:36:02 AM UTC 24 |
| Peak memory | 225372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23711695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.23711695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3150085048 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 763341266 ps |
| CPU time | 14.57 seconds |
| Started | Oct 15 12:35:56 AM UTC 24 |
| Finished | Oct 15 12:36:12 AM UTC 24 |
| Peak memory | 225572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150085048 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3150085048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2012557336 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 6045641944 ps |
| CPU time | 74.95 seconds |
| Started | Oct 15 12:36:00 AM UTC 24 |
| Finished | Oct 15 12:37:17 AM UTC 24 |
| Peak memory | 229440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012557336 -ass ert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.2012557336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3855599390 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2164610934 ps |
| CPU time | 39.9 seconds |
| Started | Oct 15 12:36:10 AM UTC 24 |
| Finished | Oct 15 12:36:51 AM UTC 24 |
| Peak memory | 215056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855599390 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3855599390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3643309971 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 66822464 ps |
| CPU time | 2.42 seconds |
| Started | Oct 15 12:36:08 AM UTC 24 |
| Finished | Oct 15 12:36:12 AM UTC 24 |
| Peak memory | 225528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643309971 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3643309971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1331377450 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 113614094 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 12:36:10 AM UTC 24 |
| Finished | Oct 15 12:36:13 AM UTC 24 |
| Peak memory | 227464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1331377450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_r and_reset.1331377450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.2594427308 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 666121242 ps |
| CPU time | 3.35 seconds |
| Started | Oct 15 12:36:08 AM UTC 24 |
| Finished | Oct 15 12:36:13 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594427308 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2594427308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3205709129 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 225601646484 ps |
| CPU time | 132.89 seconds |
| Started | Oct 15 12:36:04 AM UTC 24 |
| Finished | Oct 15 12:38:19 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205709129 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.3205709129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2754616141 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 20660420345 ps |
| CPU time | 43.45 seconds |
| Started | Oct 15 12:36:03 AM UTC 24 |
| Finished | Oct 15 12:36:48 AM UTC 24 |
| Peak memory | 215136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754616141 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.2754616141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2277563126 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4444139834 ps |
| CPU time | 11.36 seconds |
| Started | Oct 15 12:36:03 AM UTC 24 |
| Finished | Oct 15 12:36:15 AM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277563126 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.2277563126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1036942600 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 7388771068 ps |
| CPU time | 24.98 seconds |
| Started | Oct 15 12:36:03 AM UTC 24 |
| Finished | Oct 15 12:36:29 AM UTC 24 |
| Peak memory | 215028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036942600 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1036942600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3391251735 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 244285177 ps |
| CPU time | 1.81 seconds |
| Started | Oct 15 12:36:03 AM UTC 24 |
| Finished | Oct 15 12:36:05 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391251735 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.3391251735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.986666561 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3966340620 ps |
| CPU time | 6.48 seconds |
| Started | Oct 15 12:36:02 AM UTC 24 |
| Finished | Oct 15 12:36:09 AM UTC 24 |
| Peak memory | 214960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986666561 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.986666561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3718050510 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 242895806 ps |
| CPU time | 2.23 seconds |
| Started | Oct 15 12:36:01 AM UTC 24 |
| Finished | Oct 15 12:36:05 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718050510 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.3718050510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3770946698 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 144225712 ps |
| CPU time | 1.64 seconds |
| Started | Oct 15 12:36:02 AM UTC 24 |
| Finished | Oct 15 12:36:04 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770946698 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3770946698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3729928984 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 90859386 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 12:36:07 AM UTC 24 |
| Finished | Oct 15 12:36:09 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729928984 -assert nopostproc +UVM _TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.3729928984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.4016668152 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 26043975 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 12:36:07 AM UTC 24 |
| Finished | Oct 15 12:36:09 AM UTC 24 |
| Peak memory | 214588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016668152 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.4016668152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3778192988 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2075888103 ps |
| CPU time | 8.7 seconds |
| Started | Oct 15 12:36:10 AM UTC 24 |
| Finished | Oct 15 12:36:19 AM UTC 24 |
| Peak memory | 215336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778192988 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.3778192988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.3959440077 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 151319887 ps |
| CPU time | 2.59 seconds |
| Started | Oct 15 12:36:06 AM UTC 24 |
| Finished | Oct 15 12:36:10 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959440077 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3959440077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3454784235 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 454000660 ps |
| CPU time | 10.04 seconds |
| Started | Oct 15 12:36:06 AM UTC 24 |
| Finished | Oct 15 12:36:17 AM UTC 24 |
| Peak memory | 225252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454784235 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3454784235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.994305846 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 108614529 ps |
| CPU time | 5.2 seconds |
| Started | Oct 15 12:36:16 AM UTC 24 |
| Finished | Oct 15 12:36:23 AM UTC 24 |
| Peak memory | 231488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=994305846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_ra nd_reset.994305846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.3679371866 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 61358111 ps |
| CPU time | 2.29 seconds |
| Started | Oct 15 12:36:14 AM UTC 24 |
| Finished | Oct 15 12:36:18 AM UTC 24 |
| Peak memory | 225248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679371866 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3679371866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2991666234 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 7596795074 ps |
| CPU time | 33.05 seconds |
| Started | Oct 15 12:36:13 AM UTC 24 |
| Finished | Oct 15 12:36:47 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991666234 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.2991666234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3538033853 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3008970214 ps |
| CPU time | 10 seconds |
| Started | Oct 15 12:36:11 AM UTC 24 |
| Finished | Oct 15 12:36:22 AM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538033853 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3538033853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3897158794 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 109562484 ps |
| CPU time | 1.43 seconds |
| Started | Oct 15 12:36:11 AM UTC 24 |
| Finished | Oct 15 12:36:13 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897158794 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3897158794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3120995853 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1548066035 ps |
| CPU time | 10.67 seconds |
| Started | Oct 15 12:36:15 AM UTC 24 |
| Finished | Oct 15 12:36:27 AM UTC 24 |
| Peak memory | 215336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120995853 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.3120995853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1105967540 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2481111551 ps |
| CPU time | 49.29 seconds |
| Started | Oct 15 12:36:13 AM UTC 24 |
| Finished | Oct 15 12:37:04 AM UTC 24 |
| Peak memory | 227456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1105967540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_re set.1105967540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.1371064684 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 222909948 ps |
| CPU time | 6.36 seconds |
| Started | Oct 15 12:36:14 AM UTC 24 |
| Finished | Oct 15 12:36:21 AM UTC 24 |
| Peak memory | 225328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371064684 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1371064684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3801620180 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 8274387774 ps |
| CPU time | 24.92 seconds |
| Started | Oct 15 12:36:14 AM UTC 24 |
| Finished | Oct 15 12:36:40 AM UTC 24 |
| Peak memory | 225172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801620180 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3801620180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.998787598 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 157378511 ps |
| CPU time | 4.72 seconds |
| Started | Oct 15 12:36:22 AM UTC 24 |
| Finished | Oct 15 12:36:28 AM UTC 24 |
| Peak memory | 231532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=998787598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_ra nd_reset.998787598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.890549715 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 38807176 ps |
| CPU time | 2.23 seconds |
| Started | Oct 15 12:36:21 AM UTC 24 |
| Finished | Oct 15 12:36:25 AM UTC 24 |
| Peak memory | 225332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890549715 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.890549715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1403562233 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5408573494 ps |
| CPU time | 13.74 seconds |
| Started | Oct 15 12:36:18 AM UTC 24 |
| Finished | Oct 15 12:36:33 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403562233 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.1403562233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.561186731 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 6754056326 ps |
| CPU time | 17.35 seconds |
| Started | Oct 15 12:36:16 AM UTC 24 |
| Finished | Oct 15 12:36:35 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561186731 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.561186731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2000203061 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 409464969 ps |
| CPU time | 1.63 seconds |
| Started | Oct 15 12:36:16 AM UTC 24 |
| Finished | Oct 15 12:36:19 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000203061 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2000203061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3390552966 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1490782848 ps |
| CPU time | 6.03 seconds |
| Started | Oct 15 12:36:22 AM UTC 24 |
| Finished | Oct 15 12:36:29 AM UTC 24 |
| Peak memory | 215420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390552966 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.3390552966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.339059027 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 15361435513 ps |
| CPU time | 78.88 seconds |
| Started | Oct 15 12:36:19 AM UTC 24 |
| Finished | Oct 15 12:37:39 AM UTC 24 |
| Peak memory | 229484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=339059027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.339059027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2448624027 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 366452654 ps |
| CPU time | 5.48 seconds |
| Started | Oct 15 12:36:20 AM UTC 24 |
| Finished | Oct 15 12:36:27 AM UTC 24 |
| Peak memory | 225340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448624027 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2448624027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.555988683 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2338593134 ps |
| CPU time | 23.27 seconds |
| Started | Oct 15 12:36:20 AM UTC 24 |
| Finished | Oct 15 12:36:45 AM UTC 24 |
| Peak memory | 231588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555988683 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.555988683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4115672143 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 142204678 ps |
| CPU time | 3.28 seconds |
| Started | Oct 15 12:36:27 AM UTC 24 |
| Finished | Oct 15 12:36:32 AM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=4115672143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_r and_reset.4115672143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.3718117268 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 51396491 ps |
| CPU time | 1.67 seconds |
| Started | Oct 15 12:36:26 AM UTC 24 |
| Finished | Oct 15 12:36:29 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718117268 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3718117268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2283006180 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1606113067 ps |
| CPU time | 5.09 seconds |
| Started | Oct 15 12:36:24 AM UTC 24 |
| Finished | Oct 15 12:36:30 AM UTC 24 |
| Peak memory | 214880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283006180 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.2283006180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2778420766 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2106743850 ps |
| CPU time | 3.13 seconds |
| Started | Oct 15 12:36:23 AM UTC 24 |
| Finished | Oct 15 12:36:27 AM UTC 24 |
| Peak memory | 214884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778420766 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2778420766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.638799413 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 379995059 ps |
| CPU time | 2.51 seconds |
| Started | Oct 15 12:36:22 AM UTC 24 |
| Finished | Oct 15 12:36:26 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638799413 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.638799413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2703932507 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 562274462 ps |
| CPU time | 4.99 seconds |
| Started | Oct 15 12:36:27 AM UTC 24 |
| Finished | Oct 15 12:36:33 AM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703932507 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.2703932507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3535614437 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 27681047454 ps |
| CPU time | 72.61 seconds |
| Started | Oct 15 12:36:24 AM UTC 24 |
| Finished | Oct 15 12:37:39 AM UTC 24 |
| Peak memory | 232060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3535614437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_re set.3535614437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.3765479412 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 313466861 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 12:36:25 AM UTC 24 |
| Finished | Oct 15 12:36:31 AM UTC 24 |
| Peak memory | 225380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765479412 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3765479412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1800984866 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2846801337 ps |
| CPU time | 11.47 seconds |
| Started | Oct 15 12:36:26 AM UTC 24 |
| Finished | Oct 15 12:36:39 AM UTC 24 |
| Peak memory | 225376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800984866 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1800984866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1249512373 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 238709744 ps |
| CPU time | 3.77 seconds |
| Started | Oct 15 12:36:32 AM UTC 24 |
| Finished | Oct 15 12:36:37 AM UTC 24 |
| Peak memory | 229160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_sc b=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_se ed=1249512373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_r and_reset.1249512373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.569393591 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 140656198 ps |
| CPU time | 3.63 seconds |
| Started | Oct 15 12:36:31 AM UTC 24 |
| Finished | Oct 15 12:36:36 AM UTC 24 |
| Peak memory | 225524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569393591 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/r v_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.569393591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4135144273 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 49084127851 ps |
| CPU time | 103.09 seconds |
| Started | Oct 15 12:36:29 AM UTC 24 |
| Finished | Oct 15 12:38:14 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135144273 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.4135144273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2226186792 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1207944295 ps |
| CPU time | 2.34 seconds |
| Started | Oct 15 12:36:29 AM UTC 24 |
| Finished | Oct 15 12:36:32 AM UTC 24 |
| Peak memory | 214964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226186792 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2226186792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.943322235 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 521193309 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 12:36:29 AM UTC 24 |
| Finished | Oct 15 12:36:31 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943322235 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.943322235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1810204676 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 728387698 ps |
| CPU time | 6.34 seconds |
| Started | Oct 15 12:36:31 AM UTC 24 |
| Finished | Oct 15 12:36:39 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810204676 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.1810204676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.947605910 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2553748269 ps |
| CPU time | 54.78 seconds |
| Started | Oct 15 12:36:30 AM UTC 24 |
| Finished | Oct 15 12:37:26 AM UTC 24 |
| Peak memory | 232288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=947605910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.947605910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1870654577 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 436850675 ps |
| CPU time | 4.01 seconds |
| Started | Oct 15 12:36:30 AM UTC 24 |
| Finished | Oct 15 12:36:35 AM UTC 24 |
| Peak memory | 225356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870654577 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1870654577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2750016558 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2355716647 ps |
| CPU time | 8.12 seconds |
| Started | Oct 15 12:36:30 AM UTC 24 |
| Finished | Oct 15 12:36:39 AM UTC 24 |
| Peak memory | 225444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750016558 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2750016558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.2563517416 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 104581318 ps |
| CPU time | 1.99 seconds |
| Started | Oct 15 12:36:36 AM UTC 24 |
| Finished | Oct 15 12:36:39 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563517416 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2563517416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.250943538 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 6622108942 ps |
| CPU time | 21.59 seconds |
| Started | Oct 15 12:36:33 AM UTC 24 |
| Finished | Oct 15 12:36:56 AM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250943538 -assert nopostpro c +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.250943538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1451882428 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2574955870 ps |
| CPU time | 6.77 seconds |
| Started | Oct 15 12:36:33 AM UTC 24 |
| Finished | Oct 15 12:36:41 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451882428 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1451882428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.756357792 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 288519786 ps |
| CPU time | 1.21 seconds |
| Started | Oct 15 12:36:32 AM UTC 24 |
| Finished | Oct 15 12:36:35 AM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756357792 -assert nopostproc +UVM_TESTNAME=rv_dm_b ase_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.756357792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1754674895 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 282101673 ps |
| CPU time | 7.31 seconds |
| Started | Oct 15 12:36:36 AM UTC 24 |
| Finished | Oct 15 12:36:44 AM UTC 24 |
| Peak memory | 215144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754674895 -assert nopostproc +U VM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.1754674895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4153411075 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3336923994 ps |
| CPU time | 79.28 seconds |
| Started | Oct 15 12:36:34 AM UTC 24 |
| Finished | Oct 15 12:37:56 AM UTC 24 |
| Peak memory | 232344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_ scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4153411075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_re set.4153411075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2355979742 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 116843185 ps |
| CPU time | 6.32 seconds |
| Started | Oct 15 12:36:34 AM UTC 24 |
| Finished | Oct 15 12:36:42 AM UTC 24 |
| Peak memory | 225356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355979742 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_ dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2355979742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.217217739 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2971021233 ps |
| CPU time | 24.07 seconds |
| Started | Oct 15 12:36:34 AM UTC 24 |
| Finished | Oct 15 12:37:00 AM UTC 24 |
| Peak memory | 225436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217217739 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.217217739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.715004498 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 444685516 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715004498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.715004498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.472732675 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14273964731 ps |
| CPU time | 12.5 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:11:07 AM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472732675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.472732675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1152551129 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 213461288 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:49 AM UTC 24 |
| Peak memory | 250600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152551129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_buffered_enable.1152551129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4270499187 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1072221836 ps |
| CPU time | 1.5 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:49 AM UTC 24 |
| Peak memory | 214576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270499187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4270499187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.3674079712 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 146826710 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:56 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674079712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3674079712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1733146042 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 233905212 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:56 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733146042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1733146042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.201220640 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 83074525 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201220640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.201220640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.2521615319 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 155706521 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 237220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521615319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2521615319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.2176324436 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 238689128 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176324436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2176324436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.2435684641 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 205587455 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435684641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2435684641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.814221283 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 338867009 ps |
| CPU time | 0.83 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814221283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.814221283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.985379588 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 497944546 ps |
| CPU time | 2.07 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:53 AM UTC 24 |
| Peak memory | 214968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985379588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.985379588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2632523855 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 123189309 ps |
| CPU time | 1 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632523855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2632523855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.117406 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 425835247 ps |
| CPU time | 1.86 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.117406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.156579131 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 124394338 ps |
| CPU time | 0.75 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156579131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.156579131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.625261069 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 275774876 ps |
| CPU time | 1.39 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:56 AM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625261069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.625261069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.2639070640 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4712849788 ps |
| CPU time | 6.28 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:57 AM UTC 24 |
| Peak memory | 215744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639070640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2639070640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.287897513 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2141528586 ps |
| CPU time | 6.93 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287897513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.287897513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.1825237405 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 11159718 ps |
| CPU time | 0.63 seconds |
| Started | Oct 15 01:10:37 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825237405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_scanmode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rv_dm_scanmode.1825237405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_scanmode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2422129332 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 446177975 ps |
| CPU time | 2.13 seconds |
| Started | Oct 15 01:10:39 AM UTC 24 |
| Finished | Oct 15 01:10:54 AM UTC 24 |
| Peak memory | 256088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422129332 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2422129332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3939894861 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3453604617 ps |
| CPU time | 4.95 seconds |
| Started | Oct 15 01:10:36 AM UTC 24 |
| Finished | Oct 15 01:10:59 AM UTC 24 |
| Peak memory | 215472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939894861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3939894861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/0.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3104638600 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 121270250 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104638600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3104638600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.152000892 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 57745847 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152000892 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.152000892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.1285439591 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 25867018942 ps |
| CPU time | 76.49 seconds |
| Started | Oct 15 01:10:40 AM UTC 24 |
| Finished | Oct 15 01:12:08 AM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285439591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1285439591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.2158733534 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2486823330 ps |
| CPU time | 5.92 seconds |
| Started | Oct 15 01:10:40 AM UTC 24 |
| Finished | Oct 15 01:10:58 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158733534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2158733534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3520362638 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 207310227 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 244976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520362638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_buffered_enable.3520362638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.1615385179 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 603991154 ps |
| CPU time | 1.26 seconds |
| Started | Oct 15 01:10:40 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615385179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1615385179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.2777732271 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 703106435 ps |
| CPU time | 2.67 seconds |
| Started | Oct 15 01:10:40 AM UTC 24 |
| Finished | Oct 15 01:10:53 AM UTC 24 |
| Peak memory | 215092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777732271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2777732271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.521273299 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 34582283 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 236924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521273299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.521273299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.413130397 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 9555398673 ps |
| CPU time | 9.4 seconds |
| Started | Oct 15 01:10:39 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 225880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413130397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.413130397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3252022834 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 290351167 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252022834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3252022834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1736967979 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 245098634 ps |
| CPU time | 1 seconds |
| Started | Oct 15 01:10:48 AM UTC 24 |
| Finished | Oct 15 01:10:54 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736967979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1736967979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.533816711 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 140815882 ps |
| CPU time | 0.71 seconds |
| Started | Oct 15 01:10:42 AM UTC 24 |
| Finished | Oct 15 01:10:54 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533816711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.533816711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2207151132 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 182846717 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 01:10:51 AM UTC 24 |
| Finished | Oct 15 01:10:53 AM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207151132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2207151132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3987645635 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 426598935 ps |
| CPU time | 1.57 seconds |
| Started | Oct 15 01:10:49 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987645635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3987645635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3112236404 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 261945329 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 01:10:51 AM UTC 24 |
| Finished | Oct 15 01:10:53 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112236404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3112236404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1970802722 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 142811436 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 01:10:49 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970802722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1970802722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.779774384 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 446657927 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 01:10:40 AM UTC 24 |
| Finished | Oct 15 01:10:52 AM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779774384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.779774384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.384678116 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 531338418 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 01:10:42 AM UTC 24 |
| Finished | Oct 15 01:10:47 AM UTC 24 |
| Peak memory | 214428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384678116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.384678116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1944193657 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 687408522 ps |
| CPU time | 2.78 seconds |
| Started | Oct 15 01:10:49 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 225336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944193657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1944193657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.1564407506 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 260474302 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564407506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_d m-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1564407506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2840956454 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 102031200 ps |
| CPU time | 0.79 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840956454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_rom_read_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2840956454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2819771401 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4436621589 ps |
| CPU time | 2.4 seconds |
| Started | Oct 15 01:10:39 AM UTC 24 |
| Finished | Oct 15 01:10:54 AM UTC 24 |
| Peak memory | 215664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819771401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2819771401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.616204029 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 575250295 ps |
| CPU time | 1.69 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:56 AM UTC 24 |
| Peak memory | 254832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616204029 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.616204029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2217466220 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1361956029 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217466220 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2217466220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3569512217 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 73334102 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:26 AM UTC 24 |
| Peak memory | 214796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569512217 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3569512217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.402369490 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 33765061912 ps |
| CPU time | 110.08 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:13:16 AM UTC 24 |
| Peak memory | 225844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402369490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.402369490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.908836112 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2867622475 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:28 AM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908836112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.908836112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1982846854 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2190164852 ps |
| CPU time | 2.81 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:27 AM UTC 24 |
| Peak memory | 215464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982846854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.1982846854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.4232992294 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 9813051351 ps |
| CPU time | 13.98 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:39 AM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232992294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.4232992294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.2961962288 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 881961584 ps |
| CPU time | 4.79 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:29 AM UTC 24 |
| Peak memory | 224852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961962288 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2961962288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.1533108554 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 71565480 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 01:11:10 AM UTC 24 |
| Finished | Oct 15 01:11:21 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533108554 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1533108554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.3970999631 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 18866837340 ps |
| CPU time | 53.74 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:12:15 AM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970999631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3970999631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.895398608 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 811344037 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:27 AM UTC 24 |
| Peak memory | 214584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895398608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.895398608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.369304750 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1960105990 ps |
| CPU time | 6.36 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:31 AM UTC 24 |
| Peak memory | 215524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369304750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.369304750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.2343403392 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2683178473 ps |
| CPU time | 6.69 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:32 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343403392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2343403392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3984858088 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2677014175 ps |
| CPU time | 1.89 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:22 AM UTC 24 |
| Peak memory | 214892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984858088 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3984858088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.327599752 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 49544843 ps |
| CPU time | 0.68 seconds |
| Started | Oct 15 01:11:19 AM UTC 24 |
| Finished | Oct 15 01:11:22 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327599752 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.327599752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1650360390 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 7875551987 ps |
| CPU time | 10.83 seconds |
| Started | Oct 15 01:11:15 AM UTC 24 |
| Finished | Oct 15 01:11:27 AM UTC 24 |
| Peak memory | 226132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650360390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1650360390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.1929518816 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2528764517 ps |
| CPU time | 6.87 seconds |
| Started | Oct 15 01:11:10 AM UTC 24 |
| Finished | Oct 15 01:11:28 AM UTC 24 |
| Peak memory | 225876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929518816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1929518816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1354681393 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1941014703 ps |
| CPU time | 5.01 seconds |
| Started | Oct 15 01:11:10 AM UTC 24 |
| Finished | Oct 15 01:11:26 AM UTC 24 |
| Peak memory | 215456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354681393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.1354681393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2594239846 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2099531625 ps |
| CPU time | 2.6 seconds |
| Started | Oct 15 01:11:10 AM UTC 24 |
| Finished | Oct 15 01:11:23 AM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594239846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2594239846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.3129892159 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1633880572 ps |
| CPU time | 4.49 seconds |
| Started | Oct 15 01:11:15 AM UTC 24 |
| Finished | Oct 15 01:11:20 AM UTC 24 |
| Peak memory | 215280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129892159 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3129892159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.750091611 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 46796320 ps |
| CPU time | 0.67 seconds |
| Started | Oct 15 01:11:23 AM UTC 24 |
| Finished | Oct 15 01:11:25 AM UTC 24 |
| Peak memory | 214352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750091611 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.750091611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.3853570874 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 33069710742 ps |
| CPU time | 61.97 seconds |
| Started | Oct 15 01:11:21 AM UTC 24 |
| Finished | Oct 15 01:12:25 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853570874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3853570874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2040994536 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1916281307 ps |
| CPU time | 6.54 seconds |
| Started | Oct 15 01:11:20 AM UTC 24 |
| Finished | Oct 15 01:11:28 AM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040994536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2040994536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1059735643 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3377899585 ps |
| CPU time | 11 seconds |
| Started | Oct 15 01:11:19 AM UTC 24 |
| Finished | Oct 15 01:11:32 AM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059735643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.1059735643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.2334215322 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 9097551731 ps |
| CPU time | 27.98 seconds |
| Started | Oct 15 01:11:19 AM UTC 24 |
| Finished | Oct 15 01:11:49 AM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334215322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2334215322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1812888776 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1232646351 ps |
| CPU time | 4.79 seconds |
| Started | Oct 15 01:11:23 AM UTC 24 |
| Finished | Oct 15 01:11:29 AM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812888776 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1812888776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2110415374 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 46699824 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 01:11:24 AM UTC 24 |
| Finished | Oct 15 01:11:27 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110415374 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2110415374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.4051567304 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3726748178 ps |
| CPU time | 4.64 seconds |
| Started | Oct 15 01:11:23 AM UTC 24 |
| Finished | Oct 15 01:11:29 AM UTC 24 |
| Peak memory | 225928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051567304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.4051567304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.894260808 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1299251675 ps |
| CPU time | 5.33 seconds |
| Started | Oct 15 01:11:23 AM UTC 24 |
| Finished | Oct 15 01:11:30 AM UTC 24 |
| Peak memory | 215024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894260808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.894260808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2834738477 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2370208391 ps |
| CPU time | 6.41 seconds |
| Started | Oct 15 01:11:23 AM UTC 24 |
| Finished | Oct 15 01:11:31 AM UTC 24 |
| Peak memory | 215672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834738477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.2834738477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.4119621833 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 7142762595 ps |
| CPU time | 13.24 seconds |
| Started | Oct 15 01:11:23 AM UTC 24 |
| Finished | Oct 15 01:11:38 AM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119621833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4119621833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2421010551 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1925304792 ps |
| CPU time | 2.71 seconds |
| Started | Oct 15 01:11:23 AM UTC 24 |
| Finished | Oct 15 01:11:27 AM UTC 24 |
| Peak memory | 215288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421010551 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2421010551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.948813730 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 39805077 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 01:11:25 AM UTC 24 |
| Finished | Oct 15 01:11:27 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948813730 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.948813730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.775584652 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 13983157431 ps |
| CPU time | 46.6 seconds |
| Started | Oct 15 01:11:24 AM UTC 24 |
| Finished | Oct 15 01:12:12 AM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775584652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.775584652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2387622138 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1326504027 ps |
| CPU time | 2.32 seconds |
| Started | Oct 15 01:11:24 AM UTC 24 |
| Finished | Oct 15 01:11:28 AM UTC 24 |
| Peak memory | 215784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387622138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2387622138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1891891315 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1848313420 ps |
| CPU time | 6.71 seconds |
| Started | Oct 15 01:11:24 AM UTC 24 |
| Finished | Oct 15 01:11:33 AM UTC 24 |
| Peak memory | 215452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891891315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.1891891315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1356405300 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 769391410 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 01:11:24 AM UTC 24 |
| Finished | Oct 15 01:11:26 AM UTC 24 |
| Peak memory | 214484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356405300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1356405300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1951719138 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 127223126 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 01:11:26 AM UTC 24 |
| Finished | Oct 15 01:11:29 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951719138 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1951719138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4134295651 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4768726360 ps |
| CPU time | 17.3 seconds |
| Started | Oct 15 01:11:26 AM UTC 24 |
| Finished | Oct 15 01:11:45 AM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134295651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4134295651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3989310296 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 6961649841 ps |
| CPU time | 21.02 seconds |
| Started | Oct 15 01:11:26 AM UTC 24 |
| Finished | Oct 15 01:11:49 AM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989310296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3989310296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3592304876 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2961502440 ps |
| CPU time | 6.57 seconds |
| Started | Oct 15 01:11:26 AM UTC 24 |
| Finished | Oct 15 01:11:34 AM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592304876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.3592304876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.3224141961 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2905428321 ps |
| CPU time | 3.87 seconds |
| Started | Oct 15 01:11:25 AM UTC 24 |
| Finished | Oct 15 01:11:30 AM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224141961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3224141961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3379840230 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1365355469 ps |
| CPU time | 5.83 seconds |
| Started | Oct 15 01:11:26 AM UTC 24 |
| Finished | Oct 15 01:11:34 AM UTC 24 |
| Peak memory | 225264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379840230 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3379840230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.4152511508 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 103984095 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 01:11:28 AM UTC 24 |
| Finished | Oct 15 01:11:30 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152511508 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4152511508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1962849841 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 4352294663 ps |
| CPU time | 6.92 seconds |
| Started | Oct 15 01:11:28 AM UTC 24 |
| Finished | Oct 15 01:11:35 AM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962849841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1962849841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.1467525877 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 10428643230 ps |
| CPU time | 25.91 seconds |
| Started | Oct 15 01:11:27 AM UTC 24 |
| Finished | Oct 15 01:11:55 AM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467525877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1467525877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2311357191 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2439240648 ps |
| CPU time | 2.73 seconds |
| Started | Oct 15 01:11:27 AM UTC 24 |
| Finished | Oct 15 01:11:31 AM UTC 24 |
| Peak memory | 215956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311357191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.2311357191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.1034192822 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2646129923 ps |
| CPU time | 5.53 seconds |
| Started | Oct 15 01:11:26 AM UTC 24 |
| Finished | Oct 15 01:11:33 AM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034192822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1034192822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.1382388834 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 5915998858 ps |
| CPU time | 5.69 seconds |
| Started | Oct 15 01:11:28 AM UTC 24 |
| Finished | Oct 15 01:11:34 AM UTC 24 |
| Peak memory | 215544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382388834 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1382388834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.464227181 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 56380631 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:31 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464227181 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.464227181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3326066943 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 66825125974 ps |
| CPU time | 164.01 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:14:16 AM UTC 24 |
| Peak memory | 225876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326066943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3326066943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.168458234 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 6373588759 ps |
| CPU time | 20.63 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:51 AM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168458234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.168458234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.659134955 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2527700726 ps |
| CPU time | 8.56 seconds |
| Started | Oct 15 01:11:28 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659134955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.659134955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.3570167122 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 7619093082 ps |
| CPU time | 7.43 seconds |
| Started | Oct 15 01:11:28 AM UTC 24 |
| Finished | Oct 15 01:11:36 AM UTC 24 |
| Peak memory | 225876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570167122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3570167122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.741689492 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 111151214 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:32 AM UTC 24 |
| Peak memory | 214832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741689492 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.741689492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.328886484 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 7628126654 ps |
| CPU time | 10.99 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:42 AM UTC 24 |
| Peak memory | 225900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328886484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.328886484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3367789598 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1401806914 ps |
| CPU time | 4.86 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:35 AM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367789598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.3367789598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1348595167 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 6485375093 ps |
| CPU time | 20.95 seconds |
| Started | Oct 15 01:11:29 AM UTC 24 |
| Finished | Oct 15 01:11:52 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348595167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1348595167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3530809822 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 62278360 ps |
| CPU time | 0.71 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:00 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530809822 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3530809822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2602867933 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6662220790 ps |
| CPU time | 11.22 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:11:06 AM UTC 24 |
| Peak memory | 226132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602867933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2602867933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1765752033 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 12241516489 ps |
| CPU time | 19.74 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:11:14 AM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765752033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1765752033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3310241377 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 259047018 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 01:10:57 AM UTC 24 |
| Finished | Oct 15 01:10:59 AM UTC 24 |
| Peak memory | 250284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310241377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_buffered_enable.3310241377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4122850759 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 10116558378 ps |
| CPU time | 8.74 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:11:03 AM UTC 24 |
| Peak memory | 215716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122850759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.4122850759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.551391094 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 494627510 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 01:10:56 AM UTC 24 |
| Finished | Oct 15 01:10:59 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551391094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.551391094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.386882211 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 128936445 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:10:55 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386882211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.386882211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3081093125 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3192816632 ps |
| CPU time | 10.45 seconds |
| Started | Oct 15 01:10:53 AM UTC 24 |
| Finished | Oct 15 01:11:05 AM UTC 24 |
| Peak memory | 215572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081093125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3081093125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3488339316 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 271167089 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 01:10:57 AM UTC 24 |
| Finished | Oct 15 01:10:59 AM UTC 24 |
| Peak memory | 224716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488339316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sparse_lc_gate_fsm.3488339316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.534316597 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 42706881 ps |
| CPU time | 0.83 seconds |
| Started | Oct 15 01:11:30 AM UTC 24 |
| Finished | Oct 15 01:11:32 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534316597 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.534316597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3788268677 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1203521239 ps |
| CPU time | 2.79 seconds |
| Started | Oct 15 01:11:30 AM UTC 24 |
| Finished | Oct 15 01:11:34 AM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788268677 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3788268677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1998153916 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 61795859 ps |
| CPU time | 1 seconds |
| Started | Oct 15 01:11:31 AM UTC 24 |
| Finished | Oct 15 01:11:33 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998153916 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1998153916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2576849231 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 8424422112 ps |
| CPU time | 28.37 seconds |
| Started | Oct 15 01:11:31 AM UTC 24 |
| Finished | Oct 15 01:12:01 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576849231 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2576849231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2207122629 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 190575491 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 01:11:31 AM UTC 24 |
| Finished | Oct 15 01:11:33 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207122629 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2207122629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1172067305 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 7386017944 ps |
| CPU time | 10.2 seconds |
| Started | Oct 15 01:11:31 AM UTC 24 |
| Finished | Oct 15 01:11:43 AM UTC 24 |
| Peak memory | 215800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172067305 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1172067305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.3386738111 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 89857128 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 01:11:31 AM UTC 24 |
| Finished | Oct 15 01:11:34 AM UTC 24 |
| Peak memory | 214732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386738111 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3386738111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.2982591764 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2512426406 ps |
| CPU time | 4.5 seconds |
| Started | Oct 15 01:11:31 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 215728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982591764 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2982591764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2738588264 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 41922966 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 01:11:32 AM UTC 24 |
| Finished | Oct 15 01:11:38 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738588264 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2738588264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.4190222105 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2207507676 ps |
| CPU time | 5.57 seconds |
| Started | Oct 15 01:11:31 AM UTC 24 |
| Finished | Oct 15 01:11:38 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190222105 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.4190222105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3766901911 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 64969455 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 01:11:32 AM UTC 24 |
| Finished | Oct 15 01:11:38 AM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766901911 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3766901911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1055661796 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1462648977 ps |
| CPU time | 5.41 seconds |
| Started | Oct 15 01:11:32 AM UTC 24 |
| Finished | Oct 15 01:11:42 AM UTC 24 |
| Peak memory | 215304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055661796 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1055661796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.216719530 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 111041158 ps |
| CPU time | 1.3 seconds |
| Started | Oct 15 01:11:32 AM UTC 24 |
| Finished | Oct 15 01:11:38 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216719530 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.216719530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3480439804 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2343469870 ps |
| CPU time | 7.35 seconds |
| Started | Oct 15 01:11:32 AM UTC 24 |
| Finished | Oct 15 01:11:44 AM UTC 24 |
| Peak memory | 215416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480439804 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3480439804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3248824828 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 30689963 ps |
| CPU time | 0.87 seconds |
| Started | Oct 15 01:11:34 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 214324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248824828 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3248824828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1511325186 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1411688726 ps |
| CPU time | 4.8 seconds |
| Started | Oct 15 01:11:32 AM UTC 24 |
| Finished | Oct 15 01:11:42 AM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511325186 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1511325186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3391414304 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 219772138 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 01:11:34 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391414304 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3391414304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3580422687 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 29578293 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 01:11:34 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580422687 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3580422687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.1227119379 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 177424976 ps |
| CPU time | 0.85 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:00 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227119379 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1227119379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1227649374 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 51730757480 ps |
| CPU time | 39.82 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:39 AM UTC 24 |
| Peak memory | 225756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227649374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1227649374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3181503759 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 13978155111 ps |
| CPU time | 33.57 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:33 AM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181503759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3181503759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.419622812 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 10349464007 ps |
| CPU time | 2.74 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:02 AM UTC 24 |
| Peak memory | 215968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419622812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.419622812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.4185723493 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 272891333 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:00 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185723493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.4185723493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.2765667742 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 117494163 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:00 AM UTC 24 |
| Peak memory | 214948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765667742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2765667742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.2969182360 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4181295196 ps |
| CPU time | 3.78 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:03 AM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969182360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2969182360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2834656089 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2189389869 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:03 AM UTC 24 |
| Peak memory | 256276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834656089 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2834656089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2689571136 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 89685130 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:00 AM UTC 24 |
| Peak memory | 224812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689571136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sparse_lc_gate_fsm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sparse_lc_gate_fsm.2689571136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_sparse_lc_gate_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.4171445271 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 18733052322 ps |
| CPU time | 60.68 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:12:01 AM UTC 24 |
| Peak memory | 232544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=4171445271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stres s_all_with_rand_reset.4171445271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.278190996 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 76801472 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 01:11:34 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278190996 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.278190996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.1818940979 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 84929136 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 01:11:35 AM UTC 24 |
| Finished | Oct 15 01:11:38 AM UTC 24 |
| Peak memory | 214740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818940979 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1818940979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3219127481 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 75190053 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 01:11:35 AM UTC 24 |
| Finished | Oct 15 01:11:38 AM UTC 24 |
| Peak memory | 214804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219127481 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3219127481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3979592757 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2066143043 ps |
| CPU time | 2.7 seconds |
| Started | Oct 15 01:11:35 AM UTC 24 |
| Finished | Oct 15 01:11:39 AM UTC 24 |
| Peak memory | 215112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979592757 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3979592757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1293227445 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 166107231 ps |
| CPU time | 0.69 seconds |
| Started | Oct 15 01:11:35 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293227445 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1293227445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2410548354 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3197824114 ps |
| CPU time | 6.55 seconds |
| Started | Oct 15 01:11:35 AM UTC 24 |
| Finished | Oct 15 01:11:43 AM UTC 24 |
| Peak memory | 215344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410548354 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2410548354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.262058397 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 95484567 ps |
| CPU time | 0.71 seconds |
| Started | Oct 15 01:11:35 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262058397 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.262058397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1349662841 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2677750417 ps |
| CPU time | 5.85 seconds |
| Started | Oct 15 01:11:35 AM UTC 24 |
| Finished | Oct 15 01:11:43 AM UTC 24 |
| Peak memory | 215408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349662841 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1349662841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.413960948 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 33744533 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 01:11:37 AM UTC 24 |
| Finished | Oct 15 01:11:42 AM UTC 24 |
| Peak memory | 213316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413960948 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.413960948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.1611715214 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4995130495 ps |
| CPU time | 15.71 seconds |
| Started | Oct 15 01:11:37 AM UTC 24 |
| Finished | Oct 15 01:11:57 AM UTC 24 |
| Peak memory | 226120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611715214 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1611715214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.278506040 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 77964367 ps |
| CPU time | 0.83 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:46 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278506040 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.278506040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2952832481 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 130386267 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:46 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952832481 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2952832481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.2021527149 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 39059860 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:46 AM UTC 24 |
| Peak memory | 214728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021527149 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2021527149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.1140804743 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2314702452 ps |
| CPU time | 1.51 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:47 AM UTC 24 |
| Peak memory | 214864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140804743 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1140804743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.441108454 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 152540658 ps |
| CPU time | 0.79 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:46 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441108454 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.441108454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.512824415 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2754013763 ps |
| CPU time | 7.15 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:53 AM UTC 24 |
| Peak memory | 225672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512824415 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.512824415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2195942884 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 68226601 ps |
| CPU time | 0.79 seconds |
| Started | Oct 15 01:10:59 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195942884 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2195942884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.207599214 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 13548162778 ps |
| CPU time | 40.9 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:41 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207599214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.207599214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1276925422 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 596263719 ps |
| CPU time | 1.3 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 214360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276925422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1276925422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3930726267 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 280957756 ps |
| CPU time | 1.3 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 250600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930726267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_buffered_enable.3930726267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3339606754 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4184455422 ps |
| CPU time | 5.23 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:05 AM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339606754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.3339606754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2642188330 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 201587072 ps |
| CPU time | 1.3 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 214720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642188330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.2642188330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1973213598 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 164790707 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 214944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973213598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1973213598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2468293739 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2011369721 ps |
| CPU time | 3.09 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:03 AM UTC 24 |
| Peak memory | 215396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468293739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2468293739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.4040948270 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 614123445 ps |
| CPU time | 1.77 seconds |
| Started | Oct 15 01:10:58 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 254896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040948270 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4040948270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.18466663 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 158370739 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 01:11:38 AM UTC 24 |
| Finished | Oct 15 01:11:46 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18466663 -assert nopostproc +UVM_TESTNAME=rv_dm_ base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.18466663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.279139338 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 80931483 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 01:11:39 AM UTC 24 |
| Finished | Oct 15 01:11:43 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279139338 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.279139338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.1837361523 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2973124925 ps |
| CPU time | 8.99 seconds |
| Started | Oct 15 01:11:39 AM UTC 24 |
| Finished | Oct 15 01:11:51 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837361523 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1837361523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2722718204 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 98318170 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 01:11:39 AM UTC 24 |
| Finished | Oct 15 01:11:43 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722718204 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2722718204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.406163748 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5657345952 ps |
| CPU time | 17.12 seconds |
| Started | Oct 15 01:11:39 AM UTC 24 |
| Finished | Oct 15 01:11:59 AM UTC 24 |
| Peak memory | 215488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406163748 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.406163748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.1576054536 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 42455053 ps |
| CPU time | 0.8 seconds |
| Started | Oct 15 01:11:39 AM UTC 24 |
| Finished | Oct 15 01:11:42 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576054536 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1576054536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.260190410 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2316602676 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 01:11:39 AM UTC 24 |
| Finished | Oct 15 01:11:44 AM UTC 24 |
| Peak memory | 215368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260190410 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.260190410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1951396548 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 106135746 ps |
| CPU time | 0.78 seconds |
| Started | Oct 15 01:11:40 AM UTC 24 |
| Finished | Oct 15 01:11:41 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951396548 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1951396548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.384329124 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2787372605 ps |
| CPU time | 7.9 seconds |
| Started | Oct 15 01:11:39 AM UTC 24 |
| Finished | Oct 15 01:11:50 AM UTC 24 |
| Peak memory | 215816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384329124 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.384329124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.291175557 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 150104879 ps |
| CPU time | 0.77 seconds |
| Started | Oct 15 01:11:40 AM UTC 24 |
| Finished | Oct 15 01:11:41 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291175557 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.291175557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.51518127 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1682693128 ps |
| CPU time | 3.16 seconds |
| Started | Oct 15 01:11:40 AM UTC 24 |
| Finished | Oct 15 01:11:44 AM UTC 24 |
| Peak memory | 214480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51518127 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.51518127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.832326198 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 128488439 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 01:11:41 AM UTC 24 |
| Finished | Oct 15 01:11:53 AM UTC 24 |
| Peak memory | 214832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832326198 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.832326198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.1437762200 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3582805471 ps |
| CPU time | 6.45 seconds |
| Started | Oct 15 01:11:41 AM UTC 24 |
| Finished | Oct 15 01:11:48 AM UTC 24 |
| Peak memory | 215616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437762200 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1437762200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3286596662 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 65477997 ps |
| CPU time | 0.74 seconds |
| Started | Oct 15 01:11:41 AM UTC 24 |
| Finished | Oct 15 01:11:53 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286596662 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3286596662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.3022861183 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4121261366 ps |
| CPU time | 8.34 seconds |
| Started | Oct 15 01:11:41 AM UTC 24 |
| Finished | Oct 15 01:11:50 AM UTC 24 |
| Peak memory | 225732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022861183 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3022861183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.117376207 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 35878116 ps |
| CPU time | 0.65 seconds |
| Started | Oct 15 01:11:42 AM UTC 24 |
| Finished | Oct 15 01:11:54 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117376207 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.117376207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.1682303798 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 91911181 ps |
| CPU time | 0.79 seconds |
| Started | Oct 15 01:11:42 AM UTC 24 |
| Finished | Oct 15 01:11:54 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682303798 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1682303798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.3522450402 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 6238165904 ps |
| CPU time | 20.14 seconds |
| Started | Oct 15 01:11:42 AM UTC 24 |
| Finished | Oct 15 01:12:14 AM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522450402 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3522450402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2007251271 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 34796509 ps |
| CPU time | 0.86 seconds |
| Started | Oct 15 01:11:00 AM UTC 24 |
| Finished | Oct 15 01:11:02 AM UTC 24 |
| Peak memory | 214828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007251271 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2007251271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.924763800 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 8640795409 ps |
| CPU time | 24.5 seconds |
| Started | Oct 15 01:10:59 AM UTC 24 |
| Finished | Oct 15 01:11:25 AM UTC 24 |
| Peak memory | 225876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924763800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.924763800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3018320421 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 7649454633 ps |
| CPU time | 9.15 seconds |
| Started | Oct 15 01:10:59 AM UTC 24 |
| Finished | Oct 15 01:11:09 AM UTC 24 |
| Peak memory | 215568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018320421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3018320421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3721227144 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 746012603 ps |
| CPU time | 1.3 seconds |
| Started | Oct 15 01:10:59 AM UTC 24 |
| Finished | Oct 15 01:11:02 AM UTC 24 |
| Peak memory | 244856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721227144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_buffered_enable.3721227144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2865916164 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2418775216 ps |
| CPU time | 2.83 seconds |
| Started | Oct 15 01:10:59 AM UTC 24 |
| Finished | Oct 15 01:11:02 AM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865916164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.2865916164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2182212838 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 627633581 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 01:10:59 AM UTC 24 |
| Finished | Oct 15 01:11:01 AM UTC 24 |
| Peak memory | 214952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182212838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.2182212838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.4240549302 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1938068586 ps |
| CPU time | 4.84 seconds |
| Started | Oct 15 01:10:59 AM UTC 24 |
| Finished | Oct 15 01:11:05 AM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240549302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.4240549302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.122467378 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 4062474315 ps |
| CPU time | 11.94 seconds |
| Started | Oct 15 01:10:59 AM UTC 24 |
| Finished | Oct 15 01:11:13 AM UTC 24 |
| Peak memory | 225724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122467378 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.122467378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.2879608922 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 25592449318 ps |
| CPU time | 66.51 seconds |
| Started | Oct 15 01:11:00 AM UTC 24 |
| Finished | Oct 15 01:12:08 AM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879608922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2879608922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.754222265 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2272151506 ps |
| CPU time | 2.16 seconds |
| Started | Oct 15 01:11:00 AM UTC 24 |
| Finished | Oct 15 01:11:03 AM UTC 24 |
| Peak memory | 215576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754222265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.754222265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1673875083 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3074505485 ps |
| CPU time | 3.33 seconds |
| Started | Oct 15 01:11:00 AM UTC 24 |
| Finished | Oct 15 01:11:04 AM UTC 24 |
| Peak memory | 215660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673875083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1673875083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.758006160 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 71789446 ps |
| CPU time | 0.7 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:24 AM UTC 24 |
| Peak memory | 214820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758006160 -assert nopostproc +UVM_TESTNAME=rv_dm _base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.758006160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2186976933 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 345171836 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 01:11:02 AM UTC 24 |
| Finished | Oct 15 01:11:18 AM UTC 24 |
| Peak memory | 250540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186976933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_buffered_enable.2186976933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.2666624630 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2179229116 ps |
| CPU time | 4.54 seconds |
| Started | Oct 15 01:11:02 AM UTC 24 |
| Finished | Oct 15 01:11:28 AM UTC 24 |
| Peak memory | 225712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666624630 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2666624630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1003491334 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 38094959 ps |
| CPU time | 0.73 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:25 AM UTC 24 |
| Peak memory | 214824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003491334 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1003491334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1338679405 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 21856515298 ps |
| CPU time | 31.29 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:52 AM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338679405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1338679405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3595684435 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5957657930 ps |
| CPU time | 6.46 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:30 AM UTC 24 |
| Peak memory | 226216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595684435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3595684435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.1636244441 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 185812257 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:22 AM UTC 24 |
| Peak memory | 256784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636244441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_buffered_enable.1636244441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1276841628 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1437206353 ps |
| CPU time | 3.41 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:27 AM UTC 24 |
| Peak memory | 215316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276841628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.1276841628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1846008901 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1367182967 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:27 AM UTC 24 |
| Peak memory | 215536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846008901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1846008901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2207125744 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2692535381 ps |
| CPU time | 9.1 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:33 AM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207125744 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2207125744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1092462516 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1616768203 ps |
| CPU time | 21.55 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:46 AM UTC 24 |
| Peak memory | 228168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq= rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim. tcl +ntb_random_seed=1092462516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stres s_all_with_rand_reset.1092462516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3983190736 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 30247450 ps |
| CPU time | 0.72 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:25 AM UTC 24 |
| Peak memory | 214520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983190736 -assert nopostproc +UVM_TESTNAME=rv_d m_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3983190736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.4129240544 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 520003030 ps |
| CPU time | 2.06 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:26 AM UTC 24 |
| Peak memory | 245592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129240544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_buffered_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_buffered_enable.4129240544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_buffered_enable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1295448509 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 10359946649 ps |
| CPU time | 12.17 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:37 AM UTC 24 |
| Peak memory | 226020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295448509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.1295448509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.752981797 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 444241761 ps |
| CPU time | 1.61 seconds |
| Started | Oct 15 01:11:03 AM UTC 24 |
| Finished | Oct 15 01:11:26 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752981797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.752981797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1934725767 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6213709341 ps |
| CPU time | 15.58 seconds |
| Started | Oct 15 01:11:06 AM UTC 24 |
| Finished | Oct 15 01:11:36 AM UTC 24 |
| Peak memory | 215412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934725767 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1934725767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |