| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 82.47 | 96.32 | 87.13 | 92.10 | 72.50 | 90.44 | 98.21 | 40.57 |
| T312 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.761587134 | Feb 09 01:56:47 PM UTC 25 | Feb 09 01:56:50 PM UTC 25 | 45305959 ps | ||
| T313 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4126956709 | Feb 09 01:56:48 PM UTC 25 | Feb 09 01:56:51 PM UTC 25 | 194155297 ps | ||
| T103 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1096792517 | Feb 09 01:56:48 PM UTC 25 | Feb 09 01:56:53 PM UTC 25 | 288335224 ps | ||
| T102 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.988410483 | Feb 09 01:56:47 PM UTC 25 | Feb 09 01:56:54 PM UTC 25 | 847050671 ps | ||
| T104 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.734259663 | Feb 09 01:56:48 PM UTC 25 | Feb 09 01:56:55 PM UTC 25 | 487102052 ps | ||
| T314 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.868408706 | Feb 09 01:56:53 PM UTC 25 | Feb 09 01:56:56 PM UTC 25 | 728595434 ps | ||
| T315 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3785284050 | Feb 09 01:56:54 PM UTC 25 | Feb 09 01:56:56 PM UTC 25 | 381663299 ps | ||
| T316 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4060660707 | Feb 09 01:56:55 PM UTC 25 | Feb 09 01:56:58 PM UTC 25 | 1151670373 ps | ||
| T150 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2581252778 | Feb 09 01:56:51 PM UTC 25 | Feb 09 01:57:00 PM UTC 25 | 471211230 ps | ||
| T317 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2044884413 | Feb 09 01:56:46 PM UTC 25 | Feb 09 01:57:01 PM UTC 25 | 7156694848 ps | ||
| T105 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3010842781 | Feb 09 01:56:51 PM UTC 25 | Feb 09 01:57:02 PM UTC 25 | 506985757 ps | ||
| T318 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2065486853 | Feb 09 01:56:47 PM UTC 25 | Feb 09 01:57:06 PM UTC 25 | 13614523722 ps | ||
| T319 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.2232871914 | Feb 09 01:57:07 PM UTC 25 | Feb 09 01:57:09 PM UTC 25 | 107892660 ps | ||
| T320 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2100205138 | Feb 09 01:57:08 PM UTC 25 | Feb 09 01:57:11 PM UTC 25 | 65323820 ps | ||
| T144 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2923369032 | Feb 09 01:57:01 PM UTC 25 | Feb 09 01:57:11 PM UTC 25 | 567456520 ps | ||
| T115 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.67234256 | Feb 09 01:56:57 PM UTC 25 | Feb 09 01:57:14 PM UTC 25 | 5086265067 ps | ||
| T106 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3636032248 | Feb 09 01:57:10 PM UTC 25 | Feb 09 01:57:16 PM UTC 25 | 291332667 ps | ||
| T107 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1303723630 | Feb 09 01:57:12 PM UTC 25 | Feb 09 01:57:16 PM UTC 25 | 62308136 ps | ||
| T116 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2889579930 | Feb 09 01:56:46 PM UTC 25 | Feb 09 01:57:16 PM UTC 25 | 6745383247 ps | ||
| T145 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2324784068 | Feb 09 01:56:47 PM UTC 25 | Feb 09 01:57:19 PM UTC 25 | 4862961872 ps | ||
| T85 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.78249012 | Feb 09 01:56:47 PM UTC 25 | Feb 09 01:57:19 PM UTC 25 | 24591490953 ps | ||
| T321 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2285941678 | Feb 09 01:57:20 PM UTC 25 | Feb 09 01:57:23 PM UTC 25 | 254010066 ps | ||
| T322 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3463834302 | Feb 09 01:57:17 PM UTC 25 | Feb 09 01:57:23 PM UTC 25 | 607382180 ps | ||
| T108 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1214622237 | Feb 09 01:56:45 PM UTC 25 | Feb 09 01:57:24 PM UTC 25 | 2261777483 ps | ||
| T146 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2046686237 | Feb 09 01:57:17 PM UTC 25 | Feb 09 01:57:24 PM UTC 25 | 529222130 ps | ||
| T109 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.177351292 | Feb 09 01:56:48 PM UTC 25 | Feb 09 01:57:25 PM UTC 25 | 2578260619 ps | ||
| T323 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2541152633 | Feb 09 01:57:23 PM UTC 25 | Feb 09 01:57:27 PM UTC 25 | 498562451 ps | ||
| T324 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.640018527 | Feb 09 01:57:25 PM UTC 25 | Feb 09 01:57:28 PM UTC 25 | 40391551 ps | ||
| T151 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.572770509 | Feb 09 01:57:02 PM UTC 25 | Feb 09 01:57:28 PM UTC 25 | 3959936948 ps | ||
| T325 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1971378944 | Feb 09 01:56:55 PM UTC 25 | Feb 09 01:57:30 PM UTC 25 | 8517799832 ps | ||
| T110 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.263673919 | Feb 09 01:57:16 PM UTC 25 | Feb 09 01:57:30 PM UTC 25 | 618508686 ps | ||
| T326 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3257769524 | Feb 09 01:57:28 PM UTC 25 | Feb 09 01:57:31 PM UTC 25 | 129687803 ps | ||
| T327 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.312708498 | Feb 09 01:56:47 PM UTC 25 | Feb 09 01:57:31 PM UTC 25 | 19538541985 ps | ||
| T328 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1538115361 | Feb 09 01:56:57 PM UTC 25 | Feb 09 01:57:32 PM UTC 25 | 16279979119 ps | ||
| T329 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.815918599 | Feb 09 01:57:30 PM UTC 25 | Feb 09 01:57:33 PM UTC 25 | 39092611 ps | ||
| T111 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.221052051 | Feb 09 01:56:52 PM UTC 25 | Feb 09 01:57:35 PM UTC 25 | 9432381636 ps | ||
| T147 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.517788381 | Feb 09 01:57:27 PM UTC 25 | Feb 09 01:57:36 PM UTC 25 | 498665095 ps | ||
| T330 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3174115451 | Feb 09 01:56:57 PM UTC 25 | Feb 09 01:57:36 PM UTC 25 | 7285517610 ps | ||
| T112 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2013818146 | Feb 09 01:57:32 PM UTC 25 | Feb 09 01:57:37 PM UTC 25 | 149098848 ps | ||
| T119 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3505085710 | Feb 09 01:57:31 PM UTC 25 | Feb 09 01:57:37 PM UTC 25 | 135272927 ps | ||
| T331 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2936981424 | Feb 09 01:57:24 PM UTC 25 | Feb 09 01:57:38 PM UTC 25 | 1909286491 ps | ||
| T148 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.972867023 | Feb 09 01:57:34 PM UTC 25 | Feb 09 01:57:39 PM UTC 25 | 409593454 ps | ||
| T332 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.220770055 | Feb 09 01:57:37 PM UTC 25 | Feb 09 01:57:40 PM UTC 25 | 476433168 ps | ||
| T333 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.101143705 | Feb 09 01:57:37 PM UTC 25 | Feb 09 01:57:42 PM UTC 25 | 1428558343 ps | ||
| T134 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4250256359 | Feb 09 01:57:34 PM UTC 25 | Feb 09 01:57:42 PM UTC 25 | 557649507 ps | ||
| T334 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4249757111 | Feb 09 01:57:38 PM UTC 25 | Feb 09 01:57:46 PM UTC 25 | 960063533 ps | ||
| T335 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.903859720 | Feb 09 01:57:24 PM UTC 25 | Feb 09 01:57:52 PM UTC 25 | 10970865085 ps | ||
| T152 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4154409488 | Feb 09 01:57:28 PM UTC 25 | Feb 09 01:57:54 PM UTC 25 | 1261556013 ps | ||
| T117 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.354146296 | Feb 09 01:57:39 PM UTC 25 | Feb 09 01:57:56 PM UTC 25 | 4898981811 ps | ||
| T149 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.1109414101 | Feb 09 01:57:46 PM UTC 25 | Feb 09 01:57:56 PM UTC 25 | 2493790803 ps | ||
| T336 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.1524678611 | Feb 09 01:57:54 PM UTC 25 | Feb 09 01:57:57 PM UTC 25 | 52500812 ps | ||
| T337 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2764940908 | Feb 09 01:57:38 PM UTC 25 | Feb 09 01:57:58 PM UTC 25 | 5218389506 ps | ||
| T338 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.335626962 | Feb 09 01:57:40 PM UTC 25 | Feb 09 01:57:58 PM UTC 25 | 2484830869 ps | ||
| T339 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.640646036 | Feb 09 01:57:56 PM UTC 25 | Feb 09 01:57:59 PM UTC 25 | 100733177 ps | ||
| T129 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2280059329 | Feb 09 01:57:57 PM UTC 25 | Feb 09 01:58:02 PM UTC 25 | 1104124262 ps | ||
| T140 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1281681130 | Feb 09 01:57:58 PM UTC 25 | Feb 09 01:58:03 PM UTC 25 | 205410934 ps | ||
| T340 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1818366308 | Feb 09 01:57:13 PM UTC 25 | Feb 09 01:58:04 PM UTC 25 | 10346684751 ps | ||
| T341 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3997710241 | Feb 09 01:58:00 PM UTC 25 | Feb 09 01:58:04 PM UTC 25 | 176729668 ps | ||
| T135 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3710428215 | Feb 09 01:57:59 PM UTC 25 | Feb 09 01:58:06 PM UTC 25 | 495085625 ps | ||
| T342 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2477369596 | Feb 09 01:58:03 PM UTC 25 | Feb 09 01:58:06 PM UTC 25 | 472872701 ps | ||
| T343 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2774454229 | Feb 09 01:58:04 PM UTC 25 | Feb 09 01:58:07 PM UTC 25 | 248895951 ps | ||
| T344 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.649130974 | Feb 09 01:58:05 PM UTC 25 | Feb 09 01:58:10 PM UTC 25 | 1384094537 ps | ||
| T345 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2974339775 | Feb 09 01:58:05 PM UTC 25 | Feb 09 01:58:10 PM UTC 25 | 3997433075 ps | ||
| T346 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3909193973 | Feb 09 01:56:45 PM UTC 25 | Feb 09 01:58:10 PM UTC 25 | 17235835510 ps | ||
| T347 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1864596518 | Feb 09 01:58:11 PM UTC 25 | Feb 09 01:58:16 PM UTC 25 | 183474811 ps | ||
| T348 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1975639994 | Feb 09 01:58:07 PM UTC 25 | Feb 09 01:58:17 PM UTC 25 | 2118859999 ps | ||
| T349 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.718970947 | Feb 09 01:58:08 PM UTC 25 | Feb 09 01:58:17 PM UTC 25 | 13482428545 ps | ||
| T86 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1585600206 | Feb 09 01:57:26 PM UTC 25 | Feb 09 01:58:18 PM UTC 25 | 76069014575 ps | ||
| T350 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2372129199 | Feb 09 01:57:25 PM UTC 25 | Feb 09 01:58:19 PM UTC 25 | 15309756689 ps | ||
| T206 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.412816078 | Feb 09 01:57:52 PM UTC 25 | Feb 09 01:58:19 PM UTC 25 | 5766827167 ps | ||
| T351 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.585590558 | Feb 09 01:58:17 PM UTC 25 | Feb 09 01:58:20 PM UTC 25 | 71192511 ps | ||
| T352 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3308063683 | Feb 09 01:58:18 PM UTC 25 | Feb 09 01:58:21 PM UTC 25 | 59253506 ps | ||
| T353 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.4238827148 | Feb 09 01:58:20 PM UTC 25 | Feb 09 01:58:23 PM UTC 25 | 950700368 ps | ||
| T354 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3019093302 | Feb 09 01:58:19 PM UTC 25 | Feb 09 01:58:24 PM UTC 25 | 567907929 ps | ||
| T215 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2872140517 | Feb 09 01:57:00 PM UTC 25 | Feb 09 01:58:25 PM UTC 25 | 60241602491 ps | ||
| T355 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4103816525 | Feb 09 01:58:25 PM UTC 25 | Feb 09 01:58:28 PM UTC 25 | 98814093 ps | ||
| T120 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3321913048 | Feb 09 01:58:21 PM UTC 25 | Feb 09 01:58:28 PM UTC 25 | 251629512 ps | ||
| T356 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2948226838 | Feb 09 01:58:26 PM UTC 25 | Feb 09 01:58:29 PM UTC 25 | 87867624 ps | ||
| T204 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.549630397 | Feb 09 01:58:16 PM UTC 25 | Feb 09 01:58:29 PM UTC 25 | 4632136256 ps | ||
| T118 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2121208913 | Feb 09 01:58:06 PM UTC 25 | Feb 09 01:58:29 PM UTC 25 | 3594409712 ps | ||
| T357 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.935466237 | Feb 09 01:58:22 PM UTC 25 | Feb 09 01:58:30 PM UTC 25 | 370067664 ps | ||
| T358 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.3203582005 | Feb 09 01:58:30 PM UTC 25 | Feb 09 01:58:34 PM UTC 25 | 59044739 ps | ||
| T359 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3864991042 | Feb 09 01:58:29 PM UTC 25 | Feb 09 01:58:35 PM UTC 25 | 234315637 ps | ||
| T360 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3970606924 | Feb 09 01:58:34 PM UTC 25 | Feb 09 01:58:38 PM UTC 25 | 239508054 ps | ||
| T361 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2829248107 | Feb 09 01:58:31 PM UTC 25 | Feb 09 01:58:38 PM UTC 25 | 1985249653 ps | ||
| T121 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.284509520 | Feb 09 01:58:30 PM UTC 25 | Feb 09 01:58:41 PM UTC 25 | 590397210 ps | ||
| T130 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3507564888 | Feb 09 01:57:32 PM UTC 25 | Feb 09 01:58:41 PM UTC 25 | 1442613515 ps | ||
| T362 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2944614568 | Feb 09 01:58:02 PM UTC 25 | Feb 09 01:58:41 PM UTC 25 | 860282550 ps | ||
| T363 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.4143533955 | Feb 09 01:59:59 PM UTC 25 | Feb 09 02:00:03 PM UTC 25 | 129831179 ps | ||
| T364 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.693087385 | Feb 09 01:58:35 PM UTC 25 | Feb 09 01:58:43 PM UTC 25 | 1931447998 ps | ||
| T131 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.272679159 | Feb 09 01:58:42 PM UTC 25 | Feb 09 01:58:44 PM UTC 25 | 141250589 ps | ||
| T365 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2895425243 | Feb 09 01:58:38 PM UTC 25 | Feb 09 01:58:47 PM UTC 25 | 12066551058 ps | ||
| T366 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2785042084 | Feb 09 01:58:41 PM UTC 25 | Feb 09 01:58:48 PM UTC 25 | 673273998 ps | ||
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| T439 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2018820326 | Feb 09 02:00:26 PM UTC 25 | Feb 09 02:00:28 PM UTC 25 | 250865239 ps | ||
| T440 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2840934302 | Feb 09 02:00:21 PM UTC 25 | Feb 09 02:00:29 PM UTC 25 | 4216791854 ps | ||
| T441 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2795386043 | Feb 09 01:57:42 PM UTC 25 | Feb 09 02:00:29 PM UTC 25 | 66880368237 ps | ||
| T442 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2601495326 | Feb 09 01:57:20 PM UTC 25 | Feb 09 02:00:30 PM UTC 25 | 38881179498 ps | ||
| T443 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4205627900 | Feb 09 02:00:26 PM UTC 25 | Feb 09 02:00:30 PM UTC 25 | 313333207 ps | ||
| T444 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3625232021 | Feb 09 02:00:13 PM UTC 25 | Feb 09 02:00:31 PM UTC 25 | 6394712034 ps | ||
| T445 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1350739127 | Feb 09 02:00:15 PM UTC 25 | Feb 09 02:00:32 PM UTC 25 | 6207447445 ps | ||
| T126 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2128236340 | Feb 09 02:00:26 PM UTC 25 | Feb 09 02:00:32 PM UTC 25 | 194093447 ps | ||
| T446 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.609008093 | Feb 09 02:00:29 PM UTC 25 | Feb 09 02:00:34 PM UTC 25 | 97955596 ps | ||
| T447 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.977810650 | Feb 09 02:00:27 PM UTC 25 | Feb 09 02:00:34 PM UTC 25 | 2932303568 ps | ||
| T448 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4106025181 | Feb 09 02:00:31 PM UTC 25 | Feb 09 02:00:35 PM UTC 25 | 547558459 ps | ||
| T449 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.2804579930 | Feb 09 02:00:28 PM UTC 25 | Feb 09 02:00:36 PM UTC 25 | 464092704 ps | ||
| T450 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.425165165 | Feb 09 02:00:31 PM UTC 25 | Feb 09 02:00:38 PM UTC 25 | 4324959268 ps | ||
| T451 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1519726663 | Feb 09 02:00:16 PM UTC 25 | Feb 09 02:00:38 PM UTC 25 | 3514838417 ps | ||
| T452 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2180876032 | Feb 09 02:00:31 PM UTC 25 | Feb 09 02:00:38 PM UTC 25 | 179837390 ps | ||
| T453 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.2806618563 | Feb 09 02:00:34 PM UTC 25 | Feb 09 02:00:39 PM UTC 25 | 150525508 ps | ||
| T454 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1062760864 | Feb 09 02:00:35 PM UTC 25 | Feb 09 02:00:40 PM UTC 25 | 342032856 ps | ||
| T127 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.934157105 | Feb 09 02:00:30 PM UTC 25 | Feb 09 02:00:41 PM UTC 25 | 318802468 ps | ||
| T212 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1567242678 | Feb 09 02:00:13 PM UTC 25 | Feb 09 02:00:41 PM UTC 25 | 1411519252 ps | ||
| T128 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3579300476 | Feb 09 02:00:35 PM UTC 25 | Feb 09 02:00:43 PM UTC 25 | 672221414 ps | ||
| T455 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3021717802 | Feb 09 02:00:33 PM UTC 25 | Feb 09 02:00:45 PM UTC 25 | 1380533700 ps | ||
| T456 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2300136536 | Feb 09 02:00:23 PM UTC 25 | Feb 09 02:00:46 PM UTC 25 | 2769449137 ps | ||
| T457 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1521113392 | Feb 09 02:00:27 PM UTC 25 | Feb 09 02:00:50 PM UTC 25 | 7418987015 ps | ||
| T458 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.779650464 | Feb 09 01:59:59 PM UTC 25 | Feb 09 02:00:52 PM UTC 25 | 13891219879 ps | ||
| T205 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2654570836 | Feb 09 02:00:17 PM UTC 25 | Feb 09 02:00:54 PM UTC 25 | 5769293426 ps | ||
| T459 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2738294247 | Feb 09 02:00:29 PM UTC 25 | Feb 09 02:00:56 PM UTC 25 | 8544287465 ps | ||
| T460 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.832486433 | Feb 09 02:00:33 PM UTC 25 | Feb 09 02:01:00 PM UTC 25 | 2250113159 ps | ||
| T461 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.759109996 | Feb 09 02:00:32 PM UTC 25 | Feb 09 02:01:14 PM UTC 25 | 10504993481 ps | ||
| T462 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2588834017 | Feb 09 01:58:28 PM UTC 25 | Feb 09 02:01:53 PM UTC 25 | 48845416364 ps | ||
| T463 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.206781850 | Feb 09 01:59:38 PM UTC 25 | Feb 09 02:02:41 PM UTC 25 | 53191808305 ps | ||
| T464 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1703838649 | Feb 09 01:56:59 PM UTC 25 | Feb 09 02:03:08 PM UTC 25 | 115211653089 ps | ||
| T465 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3717683263 | Feb 09 01:57:42 PM UTC 25 | Feb 09 02:04:47 PM UTC 25 | 202620169296 ps | ||
| T466 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1762837539 | Feb 09 01:58:10 PM UTC 25 | Feb 09 02:04:49 PM UTC 25 | 204915067753 ps | ||
| T467 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3126203543 | Feb 09 01:58:51 PM UTC 25 | Feb 09 02:05:11 PM UTC 25 | 58383562918 ps |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.476113179 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6190205554 ps |
| CPU time | 9.51 seconds |
| Started | Feb 09 02:00:39 PM UTC 25 |
| Finished | Feb 09 02:00:49 PM UTC 25 |
| Peak memory | 216284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476113179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fs m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 0.rv_dm_tap_fsm.476113179 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2589069845 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1048056537 ps |
| CPU time | 1.58 seconds |
| Started | Feb 09 02:00:48 PM UTC 25 |
| Finished | Feb 09 02:00:51 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589069845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_ resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2589069845 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2301892413 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 199374540925 ps |
| CPU time | 779.7 seconds |
| Started | Feb 09 02:02:01 PM UTC 25 |
| Finished | Feb 09 02:15:09 PM UTC 25 |
| Peak memory | 245860 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2301892413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.2301892413 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.864359495 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8767431495 ps |
| CPU time | 58.52 seconds |
| Started | Feb 09 02:00:40 PM UTC 25 |
| Finished | Feb 09 02:01:40 PM UTC 25 |
| Peak memory | 226540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864359495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sb a_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.864359495 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.2491407117 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4831274121 ps |
| CPU time | 28.42 seconds |
| Started | Feb 09 02:01:13 PM UTC 25 |
| Finished | Feb 09 02:01:43 PM UTC 25 |
| Peak memory | 226444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491407117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2491407117 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.774849801 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 632094768 ps |
| CPU time | 1.59 seconds |
| Started | Feb 09 02:01:09 PM UTC 25 |
| Finished | Feb 09 02:01:11 PM UTC 25 |
| Peak memory | 253584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774849801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.774849801 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2324784068 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4862961872 ps |
| CPU time | 30.05 seconds |
| Started | Feb 09 01:56:47 PM UTC 25 |
| Finished | Feb 09 01:57:19 PM UTC 25 |
| Peak memory | 225784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324784068 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2324784068 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2277188597 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 99142123 ps |
| CPU time | 1.53 seconds |
| Started | Feb 09 02:00:53 PM UTC 25 |
| Finished | Feb 09 02:00:55 PM UTC 25 |
| Peak memory | 214732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277188597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_f ailed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2277188597 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1599876082 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 132212986085 ps |
| CPU time | 117.5 seconds |
| Started | Feb 09 02:01:36 PM UTC 25 |
| Finished | Feb 09 02:03:36 PM UTC 25 |
| Peak memory | 232588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599876082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1599876082 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2043718837 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4219963380 ps |
| CPU time | 17.03 seconds |
| Started | Feb 09 02:00:53 PM UTC 25 |
| Finished | Feb 09 02:01:11 PM UTC 25 |
| Peak memory | 226604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043718837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2043718837 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.177449669 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4222839450 ps |
| CPU time | 22.42 seconds |
| Started | Feb 09 02:02:05 PM UTC 25 |
| Finished | Feb 09 02:02:29 PM UTC 25 |
| Peak memory | 226444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177449669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.177449669 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1821280097 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 86661943 ps |
| CPU time | 1.1 seconds |
| Started | Feb 09 02:00:55 PM UTC 25 |
| Finished | Feb 09 02:00:57 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821280097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1821280097 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.732687478 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3927265183 ps |
| CPU time | 12.66 seconds |
| Started | Feb 09 02:01:02 PM UTC 25 |
| Finished | Feb 09 02:01:16 PM UTC 25 |
| Peak memory | 216096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732687478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_de bug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.732687478 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.770579637 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 395140794 ps |
| CPU time | 2.98 seconds |
| Started | Feb 09 02:00:43 PM UTC 25 |
| Finished | Feb 09 02:00:47 PM UTC 25 |
| Peak memory | 215700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770579637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr _exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -c m_log /dev/null -cm_name 0.rv_dm_cmderr_exception.770579637 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1533430602 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3541632349 ps |
| CPU time | 9.54 seconds |
| Started | Feb 09 02:01:54 PM UTC 25 |
| Finished | Feb 09 02:02:05 PM UTC 25 |
| Peak memory | 226512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533430602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1533430602 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1214622237 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2261777483 ps |
| CPU time | 37.18 seconds |
| Started | Feb 09 01:56:45 PM UTC 25 |
| Finished | Feb 09 01:57:24 PM UTC 25 |
| Peak memory | 215480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214622237 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_aliasing.1214622237 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2176585677 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 322733636645 ps |
| CPU time | 2406.94 seconds |
| Started | Feb 09 02:01:14 PM UTC 25 |
| Finished | Feb 09 02:41:47 PM UTC 25 |
| Peak memory | 260184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2176585677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.2176585677 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4278428303 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 40919613081 ps |
| CPU time | 144.27 seconds |
| Started | Feb 09 02:02:44 PM UTC 25 |
| Finished | Feb 09 02:05:11 PM UTC 25 |
| Peak memory | 226424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278428303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4278428303 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.1876766762 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 8727669677 ps |
| CPU time | 21.34 seconds |
| Started | Feb 09 02:02:30 PM UTC 25 |
| Finished | Feb 09 02:02:53 PM UTC 25 |
| Peak memory | 226444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876766762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1876766762 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.970172436 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 8372482194 ps |
| CPU time | 28.46 seconds |
| Started | Feb 09 02:03:06 PM UTC 25 |
| Finished | Feb 09 02:03:35 PM UTC 25 |
| Peak memory | 226336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970172436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.970172436 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.364935057 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 62411567 ps |
| CPU time | 1.51 seconds |
| Started | Feb 09 02:00:52 PM UTC 25 |
| Finished | Feb 09 02:00:54 PM UTC 25 |
| Peak memory | 224788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364935057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_re ad_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.rv_dm_rom_read_access.364935057 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.2033360981 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7545604247 ps |
| CPU time | 6.93 seconds |
| Started | Feb 09 02:03:12 PM UTC 25 |
| Finished | Feb 09 02:03:21 PM UTC 25 |
| Peak memory | 226420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033360981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2033360981 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1518409067 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 73176313 ps |
| CPU time | 1.42 seconds |
| Started | Feb 09 02:00:53 PM UTC 25 |
| Finished | Feb 09 02:00:55 PM UTC 25 |
| Peak memory | 214988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518409067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_harts el_warl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.rv_dm_hartsel_warl.1518409067 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_hartsel_warl/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.572770509 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3959936948 ps |
| CPU time | 24.02 seconds |
| Started | Feb 09 01:57:02 PM UTC 25 |
| Finished | Feb 09 01:57:28 PM UTC 25 |
| Peak memory | 232668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572770509 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.572770509 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.4189612210 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 86641848 ps |
| CPU time | 2.5 seconds |
| Started | Feb 09 01:59:30 PM UTC 25 |
| Finished | Feb 09 01:59:33 PM UTC 25 |
| Peak memory | 225648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189612210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4189612210 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1062939061 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 929336636 ps |
| CPU time | 3.72 seconds |
| Started | Feb 09 02:00:47 PM UTC 25 |
| Finished | Feb 09 02:00:52 PM UTC 25 |
| Peak memory | 216024 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062939061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmder r_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1062939061 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2223713213 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 876803312 ps |
| CPU time | 2.22 seconds |
| Started | Feb 09 01:56:46 PM UTC 25 |
| Finished | Feb 09 01:56:49 PM UTC 25 |
| Peak memory | 214880 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223713213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_aliasing.2223713213 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.2032060874 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 404868543 ps |
| CPU time | 1.16 seconds |
| Started | Feb 09 02:00:52 PM UTC 25 |
| Finished | Feb 09 02:00:54 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032060874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstr actcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2032060874 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.1637677186 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 66926876 ps |
| CPU time | 1.3 seconds |
| Started | Feb 09 02:01:07 PM UTC 25 |
| Finished | Feb 09 02:01:10 PM UTC 25 |
| Peak memory | 237396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637677186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug _disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.rv_dm_debug_disabled.1637677186 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.4067317787 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4794823771 ps |
| CPU time | 25.56 seconds |
| Started | Feb 09 02:02:57 PM UTC 25 |
| Finished | Feb 09 02:03:24 PM UTC 25 |
| Peak memory | 226236 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067317787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4067317787 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3765127645 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4527930314 ps |
| CPU time | 15.17 seconds |
| Started | Feb 09 02:02:57 PM UTC 25 |
| Finished | Feb 09 02:03:13 PM UTC 25 |
| Peak memory | 226560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765127645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3765127645 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.1558204855 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2724682641 ps |
| CPU time | 6.13 seconds |
| Started | Feb 09 02:03:19 PM UTC 25 |
| Finished | Feb 09 02:03:27 PM UTC 25 |
| Peak memory | 216108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558204855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1558204855 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1194806234 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 272577791 ps |
| CPU time | 1.49 seconds |
| Started | Feb 09 02:01:26 PM UTC 25 |
| Finished | Feb 09 02:01:29 PM UTC 25 |
| Peak memory | 214988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194806234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_ unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 4.rv_dm_hart_unavail.1194806234 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.297135172 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2496428551 ps |
| CPU time | 9.79 seconds |
| Started | Feb 09 02:03:24 PM UTC 25 |
| Finished | Feb 09 02:03:35 PM UTC 25 |
| Peak memory | 226440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297135172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.297135172 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.2840637636 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2340556868 ps |
| CPU time | 11.5 seconds |
| Started | Feb 09 02:03:25 PM UTC 25 |
| Finished | Feb 09 02:03:38 PM UTC 25 |
| Peak memory | 226348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840637636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2840637636 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.2627370640 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2842398061 ps |
| CPU time | 4.7 seconds |
| Started | Feb 09 02:01:47 PM UTC 25 |
| Finished | Feb 09 02:01:53 PM UTC 25 |
| Peak memory | 226480 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627370640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2627370640 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2889579930 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 6745383247 ps |
| CPU time | 28.89 seconds |
| Started | Feb 09 01:56:46 PM UTC 25 |
| Finished | Feb 09 01:57:16 PM UTC 25 |
| Peak memory | 215420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889579930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_hw_reset.2889579930 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3010842781 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 506985757 ps |
| CPU time | 10.04 seconds |
| Started | Feb 09 01:56:51 PM UTC 25 |
| Finished | Feb 09 01:57:02 PM UTC 25 |
| Peak memory | 215356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010842781 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_csr_outstanding.3010842781 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2386371965 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 389561778 ps |
| CPU time | 1.71 seconds |
| Started | Feb 09 02:00:49 PM UTC 25 |
| Finished | Feb 09 02:00:52 PM UTC 25 |
| Peak memory | 224784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386371965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmre set_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.rv_dm_ndmreset_req.2386371965 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2872140517 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 60241602491 ps |
| CPU time | 82.62 seconds |
| Started | Feb 09 01:57:00 PM UTC 25 |
| Finished | Feb 09 01:58:25 PM UTC 25 |
| Peak memory | 243148 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287214 0517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2872140517 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2753182130 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1234817874 ps |
| CPU time | 22.21 seconds |
| Started | Feb 09 01:59:29 PM UTC 25 |
| Finished | Feb 09 01:59:52 PM UTC 25 |
| Peak memory | 225592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753182130 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2753182130 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3441300837 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3406278806 ps |
| CPU time | 20.98 seconds |
| Started | Feb 09 01:59:46 PM UTC 25 |
| Finished | Feb 09 02:00:09 PM UTC 25 |
| Peak memory | 232728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441300837 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3441300837 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3533732167 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 948659379 ps |
| CPU time | 2.16 seconds |
| Started | Feb 09 02:00:37 PM UTC 25 |
| Finished | Feb 09 02:00:41 PM UTC 25 |
| Peak memory | 216032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533732167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 0.rv_dm_smoke.3533732167 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2939836115 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2213601728 ps |
| CPU time | 15.94 seconds |
| Started | Feb 09 02:02:15 PM UTC 25 |
| Finished | Feb 09 02:02:33 PM UTC 25 |
| Peak memory | 226348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939836115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2939836115 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.1766860363 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1379660930 ps |
| CPU time | 10.18 seconds |
| Started | Feb 09 02:02:22 PM UTC 25 |
| Finished | Feb 09 02:02:33 PM UTC 25 |
| Peak memory | 226304 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766860363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1766860363 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1285493755 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1939255910 ps |
| CPU time | 12.01 seconds |
| Started | Feb 09 02:03:08 PM UTC 25 |
| Finished | Feb 09 02:03:21 PM UTC 25 |
| Peak memory | 215980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285493755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1285493755 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2802255606 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3712316035 ps |
| CPU time | 4.15 seconds |
| Started | Feb 09 02:01:20 PM UTC 25 |
| Finished | Feb 09 02:01:25 PM UTC 25 |
| Peak memory | 216112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802255606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2802255606 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3498658708 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 5628659244 ps |
| CPU time | 3.66 seconds |
| Started | Feb 09 02:03:29 PM UTC 25 |
| Finished | Feb 09 02:03:34 PM UTC 25 |
| Peak memory | 216176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498658708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3498658708 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/45.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.2017632538 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1474615629 ps |
| CPU time | 6.91 seconds |
| Started | Feb 09 02:03:30 PM UTC 25 |
| Finished | Feb 09 02:03:38 PM UTC 25 |
| Peak memory | 216048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017632538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2017632538 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/46.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.3278932864 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3148714020 ps |
| CPU time | 4.87 seconds |
| Started | Feb 09 02:01:52 PM UTC 25 |
| Finished | Feb 09 02:01:58 PM UTC 25 |
| Peak memory | 216216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278932864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 8.rv_dm_sba_tl_access.3278932864 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2006234611 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 6151838518 ps |
| CPU time | 16.63 seconds |
| Started | Feb 09 02:01:58 PM UTC 25 |
| Finished | Feb 09 02:02:16 PM UTC 25 |
| Peak memory | 226684 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006234611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2006234611 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2654570836 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5769293426 ps |
| CPU time | 35.28 seconds |
| Started | Feb 09 02:00:17 PM UTC 25 |
| Finished | Feb 09 02:00:54 PM UTC 25 |
| Peak memory | 225776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654570836 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2654570836 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.1221418505 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 379996244 ps |
| CPU time | 1.47 seconds |
| Started | Feb 09 02:00:42 PM UTC 25 |
| Finished | Feb 09 02:00:44 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221418505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmder r_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1221418505 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.2906493645 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 426053240 ps |
| CPU time | 1.24 seconds |
| Started | Feb 09 02:00:46 PM UTC 25 |
| Finished | Feb 09 02:00:49 PM UTC 25 |
| Peak memory | 214988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906493645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_ unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 0.rv_dm_hart_unavail.2906493645 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2434680628 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 150963954 ps |
| CPU time | 0.97 seconds |
| Started | Feb 09 02:00:51 PM UTC 25 |
| Finished | Feb 09 02:00:53 PM UTC 25 |
| Peak memory | 214884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434680628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_ dtm_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2434680628 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1268122504 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1015346948 ps |
| CPU time | 3.32 seconds |
| Started | Feb 09 02:00:53 PM UTC 25 |
| Finished | Feb 09 02:00:57 PM UTC 25 |
| Peak memory | 215768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268122504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progb uf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1268122504 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.397909550 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 615010633 ps |
| CPU time | 4.76 seconds |
| Started | Feb 09 02:00:56 PM UTC 25 |
| Finished | Feb 09 02:01:02 PM UTC 25 |
| Peak memory | 215772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397909550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr _busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.397909550 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2684375967 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 154407775 ps |
| CPU time | 1.24 seconds |
| Started | Feb 09 02:01:07 PM UTC 25 |
| Finished | Feb 09 02:01:10 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684375967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_f ailed_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.rv_dm_dmi_failed_op.2684375967 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_dmi_failed_op/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.628646149 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 132304528 ps |
| CPU time | 1.28 seconds |
| Started | Feb 09 02:01:03 PM UTC 25 |
| Finished | Feb 09 02:01:05 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628646149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_d mi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.628646149 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1902734531 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4023119414 ps |
| CPU time | 8.71 seconds |
| Started | Feb 09 02:01:07 PM UTC 25 |
| Finished | Feb 09 02:01:17 PM UTC 25 |
| Peak memory | 226396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902734531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1902734531 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.2941156328 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 8351163670 ps |
| CPU time | 40.74 seconds |
| Started | Feb 09 02:02:04 PM UTC 25 |
| Finished | Feb 09 02:02:47 PM UTC 25 |
| Peak memory | 228560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941156328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2941156328 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2025777317 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4833038011 ps |
| CPU time | 6.56 seconds |
| Started | Feb 09 02:02:02 PM UTC 25 |
| Finished | Feb 09 02:02:09 PM UTC 25 |
| Peak memory | 226436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025777317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl_access.2025777317 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1496341438 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4616257721 ps |
| CPU time | 9.38 seconds |
| Started | Feb 09 02:02:11 PM UTC 25 |
| Finished | Feb 09 02:02:21 PM UTC 25 |
| Peak memory | 226336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496341438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1496341438 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1371730953 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 13181184074 ps |
| CPU time | 39.5 seconds |
| Started | Feb 09 02:02:14 PM UTC 25 |
| Finished | Feb 09 02:02:55 PM UTC 25 |
| Peak memory | 226540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371730953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_tl_access.1371730953 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3284216745 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3263081776 ps |
| CPU time | 5.11 seconds |
| Started | Feb 09 02:02:28 PM UTC 25 |
| Finished | Feb 09 02:02:35 PM UTC 25 |
| Peak memory | 226432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284216745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3284216745 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2200083061 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 5170151289 ps |
| CPU time | 11.1 seconds |
| Started | Feb 09 02:02:28 PM UTC 25 |
| Finished | Feb 09 02:02:41 PM UTC 25 |
| Peak memory | 216212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200083061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 14.rv_dm_sba_tl_access.2200083061 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1843681136 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3821251641 ps |
| CPU time | 9.24 seconds |
| Started | Feb 09 02:02:36 PM UTC 25 |
| Finished | Feb 09 02:02:46 PM UTC 25 |
| Peak memory | 216264 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843681136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 15.rv_dm_sba_tl_access.1843681136 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1277640419 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2421200464 ps |
| CPU time | 4.75 seconds |
| Started | Feb 09 02:02:40 PM UTC 25 |
| Finished | Feb 09 02:02:46 PM UTC 25 |
| Peak memory | 226408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277640419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1277640419 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1975360242 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3640931522 ps |
| CPU time | 10.75 seconds |
| Started | Feb 09 02:02:50 PM UTC 25 |
| Finished | Feb 09 02:03:02 PM UTC 25 |
| Peak memory | 226496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975360242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1975360242 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.506008538 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4535281392 ps |
| CPU time | 8.79 seconds |
| Started | Feb 09 02:02:54 PM UTC 25 |
| Finished | Feb 09 02:03:04 PM UTC 25 |
| Peak memory | 216256 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506008538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sb a_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.506008538 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.3949105975 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4484310187 ps |
| CPU time | 7.89 seconds |
| Started | Feb 09 02:02:53 PM UTC 25 |
| Finished | Feb 09 02:03:02 PM UTC 25 |
| Peak memory | 216192 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949105975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 19.rv_dm_sba_tl_access.3949105975 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2228969622 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2709165688 ps |
| CPU time | 5.43 seconds |
| Started | Feb 09 02:03:00 PM UTC 25 |
| Finished | Feb 09 02:03:07 PM UTC 25 |
| Peak memory | 226228 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228969622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2228969622 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1191472296 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 405732042 ps |
| CPU time | 1.7 seconds |
| Started | Feb 09 02:01:20 PM UTC 25 |
| Finished | Feb 09 02:01:23 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191472296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_ resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.1191472296 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.130796245 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8752920931 ps |
| CPU time | 25.92 seconds |
| Started | Feb 09 02:03:10 PM UTC 25 |
| Finished | Feb 09 02:03:37 PM UTC 25 |
| Peak memory | 216168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130796245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.130796245 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.235415833 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4847362967 ps |
| CPU time | 8.25 seconds |
| Started | Feb 09 02:03:14 PM UTC 25 |
| Finished | Feb 09 02:03:23 PM UTC 25 |
| Peak memory | 216288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235415833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.235415833 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.3271752616 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 9066289433 ps |
| CPU time | 10.22 seconds |
| Started | Feb 09 02:03:16 PM UTC 25 |
| Finished | Feb 09 02:03:27 PM UTC 25 |
| Peak memory | 216108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271752616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3271752616 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3156914794 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5525398785 ps |
| CPU time | 8.13 seconds |
| Started | Feb 09 02:03:22 PM UTC 25 |
| Finished | Feb 09 02:03:31 PM UTC 25 |
| Peak memory | 226340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156914794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3156914794 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1154293556 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2593173547 ps |
| CPU time | 13.11 seconds |
| Started | Feb 09 02:03:27 PM UTC 25 |
| Finished | Feb 09 02:03:42 PM UTC 25 |
| Peak memory | 216352 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154293556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1154293556 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.111302142 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2009939732 ps |
| CPU time | 5.83 seconds |
| Started | Feb 09 02:03:32 PM UTC 25 |
| Finished | Feb 09 02:03:39 PM UTC 25 |
| Peak memory | 226280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111302142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.111302142 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2324493402 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 4772054501 ps |
| CPU time | 3.99 seconds |
| Started | Feb 09 02:01:45 PM UTC 25 |
| Finished | Feb 09 02:01:51 PM UTC 25 |
| Peak memory | 226468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324493402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2324493402 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.25890947 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2066230419 ps |
| CPU time | 12.51 seconds |
| Started | Feb 09 02:01:46 PM UTC 25 |
| Finished | Feb 09 02:02:00 PM UTC 25 |
| Peak memory | 216112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25890947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_ access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 7.rv_dm_sba_tl_access.25890947 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.1658756777 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1998168241 ps |
| CPU time | 6.91 seconds |
| Started | Feb 09 02:01:48 PM UTC 25 |
| Finished | Feb 09 02:01:57 PM UTC 25 |
| Peak memory | 215972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658756777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1658756777 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3786649800 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 7922227677 ps |
| CPU time | 13.05 seconds |
| Started | Feb 09 02:01:55 PM UTC 25 |
| Finished | Feb 09 02:02:09 PM UTC 25 |
| Peak memory | 216292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786649800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3786649800 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.177351292 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2578260619 ps |
| CPU time | 35.34 seconds |
| Started | Feb 09 01:56:48 PM UTC 25 |
| Finished | Feb 09 01:57:25 PM UTC 25 |
| Peak memory | 225764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177351292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.177351292 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.734259663 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 487102052 ps |
| CPU time | 4.84 seconds |
| Started | Feb 09 01:56:48 PM UTC 25 |
| Finished | Feb 09 01:56:55 PM UTC 25 |
| Peak memory | 225216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734259663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.734259663 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2581252778 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 471211230 ps |
| CPU time | 8.02 seconds |
| Started | Feb 09 01:56:51 PM UTC 25 |
| Finished | Feb 09 01:57:00 PM UTC 25 |
| Peak memory | 232948 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25812527 78 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2581252778 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1096792517 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 288335224 ps |
| CPU time | 3.57 seconds |
| Started | Feb 09 01:56:48 PM UTC 25 |
| Finished | Feb 09 01:56:53 PM UTC 25 |
| Peak memory | 225712 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096792517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1096792517 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.312708498 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 19538541985 ps |
| CPU time | 42.18 seconds |
| Started | Feb 09 01:56:47 PM UTC 25 |
| Finished | Feb 09 01:57:31 PM UTC 25 |
| Peak memory | 215224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312708498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_aliasing.312708498 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2065486853 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 13614523722 ps |
| CPU time | 17.96 seconds |
| Started | Feb 09 01:56:47 PM UTC 25 |
| Finished | Feb 09 01:57:06 PM UTC 25 |
| Peak memory | 215216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065486853 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.2065486853 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2044884413 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 7156694848 ps |
| CPU time | 13.24 seconds |
| Started | Feb 09 01:56:46 PM UTC 25 |
| Finished | Feb 09 01:57:01 PM UTC 25 |
| Peak memory | 215284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044884413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2044884413 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3909193973 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 17235835510 ps |
| CPU time | 83.29 seconds |
| Started | Feb 09 01:56:45 PM UTC 25 |
| Finished | Feb 09 01:58:10 PM UTC 25 |
| Peak memory | 215288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909193973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_bit_bash.3909193973 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3146942992 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 256665897 ps |
| CPU time | 1.55 seconds |
| Started | Feb 09 01:56:45 PM UTC 25 |
| Finished | Feb 09 01:56:48 PM UTC 25 |
| Peak memory | 214356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146942992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_hw_reset.3146942992 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.751789355 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 543071806 ps |
| CPU time | 1.61 seconds |
| Started | Feb 09 01:56:45 PM UTC 25 |
| Finished | Feb 09 01:56:48 PM UTC 25 |
| Peak memory | 214096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751789355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.751789355 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4126956709 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 194155297 ps |
| CPU time | 1.19 seconds |
| Started | Feb 09 01:56:48 PM UTC 25 |
| Finished | Feb 09 01:56:51 PM UTC 25 |
| Peak memory | 212808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126956709 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_partial_access.4126956709 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.761587134 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 45305959 ps |
| CPU time | 1.22 seconds |
| Started | Feb 09 01:56:47 PM UTC 25 |
| Finished | Feb 09 01:56:50 PM UTC 25 |
| Peak memory | 214164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761587134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.761587134 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.78249012 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 24591490953 ps |
| CPU time | 30.82 seconds |
| Started | Feb 09 01:56:47 PM UTC 25 |
| Finished | Feb 09 01:57:19 PM UTC 25 |
| Peak memory | 232604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782490 12 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.78249012 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.988410483 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 847050671 ps |
| CPU time | 5.84 seconds |
| Started | Feb 09 01:56:47 PM UTC 25 |
| Finished | Feb 09 01:56:54 PM UTC 25 |
| Peak memory | 225460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988410483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_ TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cov er_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.988410483 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.221052051 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 9432381636 ps |
| CPU time | 41.97 seconds |
| Started | Feb 09 01:56:52 PM UTC 25 |
| Finished | Feb 09 01:57:35 PM UTC 25 |
| Peak memory | 225716 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221052051 -assert nopostpr oc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_aliasing.221052051 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1818366308 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 10346684751 ps |
| CPU time | 49.77 seconds |
| Started | Feb 09 01:57:13 PM UTC 25 |
| Finished | Feb 09 01:58:04 PM UTC 25 |
| Peak memory | 225968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818366308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1818366308 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3636032248 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 291332667 ps |
| CPU time | 4.05 seconds |
| Started | Feb 09 01:57:10 PM UTC 25 |
| Finished | Feb 09 01:57:16 PM UTC 25 |
| Peak memory | 225904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636032248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3636032248 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2046686237 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 529222130 ps |
| CPU time | 6.08 seconds |
| Started | Feb 09 01:57:17 PM UTC 25 |
| Finished | Feb 09 01:57:24 PM UTC 25 |
| Peak memory | 231840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20466862 37 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2046686237 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1303723630 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 62308136 ps |
| CPU time | 3.29 seconds |
| Started | Feb 09 01:57:12 PM UTC 25 |
| Finished | Feb 09 01:57:16 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303723630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1303723630 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1703838649 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 115211653089 ps |
| CPU time | 364.07 seconds |
| Started | Feb 09 01:56:59 PM UTC 25 |
| Finished | Feb 09 02:03:08 PM UTC 25 |
| Peak memory | 215608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703838649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_aliasing.1703838649 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1538115361 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 16279979119 ps |
| CPU time | 33.88 seconds |
| Started | Feb 09 01:56:57 PM UTC 25 |
| Finished | Feb 09 01:57:32 PM UTC 25 |
| Peak memory | 215284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538115361 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.1538115361 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.67234256 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 5086265067 ps |
| CPU time | 16.12 seconds |
| Started | Feb 09 01:56:57 PM UTC 25 |
| Finished | Feb 09 01:57:14 PM UTC 25 |
| Peak memory | 215056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67234256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vc s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_hw_reset.67234256 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3174115451 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 7285517610 ps |
| CPU time | 37.33 seconds |
| Started | Feb 09 01:56:57 PM UTC 25 |
| Finished | Feb 09 01:57:36 PM UTC 25 |
| Peak memory | 214816 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174115451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3174115451 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4060660707 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1151670373 ps |
| CPU time | 2.1 seconds |
| Started | Feb 09 01:56:55 PM UTC 25 |
| Finished | Feb 09 01:56:58 PM UTC 25 |
| Peak memory | 215260 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060660707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_aliasing.4060660707 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1971378944 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 8517799832 ps |
| CPU time | 33.62 seconds |
| Started | Feb 09 01:56:55 PM UTC 25 |
| Finished | Feb 09 01:57:30 PM UTC 25 |
| Peak memory | 215288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971378944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_bit_bash.1971378944 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.868408706 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 728595434 ps |
| CPU time | 2.14 seconds |
| Started | Feb 09 01:56:53 PM UTC 25 |
| Finished | Feb 09 01:56:56 PM UTC 25 |
| Peak memory | 215004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868408706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_hw_reset.868408706 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3785284050 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 381663299 ps |
| CPU time | 1.46 seconds |
| Started | Feb 09 01:56:54 PM UTC 25 |
| Finished | Feb 09 01:56:56 PM UTC 25 |
| Peak memory | 214168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785284050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3785284050 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2100205138 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 65323820 ps |
| CPU time | 1.09 seconds |
| Started | Feb 09 01:57:08 PM UTC 25 |
| Finished | Feb 09 01:57:11 PM UTC 25 |
| Peak memory | 214160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100205138 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_partial_access.2100205138 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.2232871914 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 107892660 ps |
| CPU time | 1.09 seconds |
| Started | Feb 09 01:57:07 PM UTC 25 |
| Finished | Feb 09 01:57:09 PM UTC 25 |
| Peak memory | 214164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232871914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2232871914 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.263673919 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 618508686 ps |
| CPU time | 13.35 seconds |
| Started | Feb 09 01:57:16 PM UTC 25 |
| Finished | Feb 09 01:57:30 PM UTC 25 |
| Peak memory | 215424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263673919 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr_outstanding.263673919 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2923369032 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 567456520 ps |
| CPU time | 8.86 seconds |
| Started | Feb 09 01:57:01 PM UTC 25 |
| Finished | Feb 09 01:57:11 PM UTC 25 |
| Peak memory | 225644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923369032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2923369032 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3713249453 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 351559714 ps |
| CPU time | 3.47 seconds |
| Started | Feb 09 01:59:34 PM UTC 25 |
| Finished | Feb 09 01:59:38 PM UTC 25 |
| Peak memory | 230136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37132494 53 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3713249453 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.452953217 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2458155538 ps |
| CPU time | 8.12 seconds |
| Started | Feb 09 01:59:27 PM UTC 25 |
| Finished | Feb 09 01:59:37 PM UTC 25 |
| Peak memory | 215360 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452953217 -assert nopostproc +UVM_TEST NAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_bit_bash.452953217 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2853649553 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 11589276054 ps |
| CPU time | 18.03 seconds |
| Started | Feb 09 01:59:27 PM UTC 25 |
| Finished | Feb 09 01:59:47 PM UTC 25 |
| Peak memory | 215168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853649553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.2853649553 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1160607965 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 287208335 ps |
| CPU time | 1.44 seconds |
| Started | Feb 09 01:59:25 PM UTC 25 |
| Finished | Feb 09 01:59:28 PM UTC 25 |
| Peak memory | 214100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160607965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.1160607965 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.325199697 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 177104294 ps |
| CPU time | 5.45 seconds |
| Started | Feb 09 01:59:34 PM UTC 25 |
| Finished | Feb 09 01:59:40 PM UTC 25 |
| Peak memory | 215416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325199697 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_csr_outstanding.325199697 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1817445440 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 333927248 ps |
| CPU time | 4.72 seconds |
| Started | Feb 09 01:59:28 PM UTC 25 |
| Finished | Feb 09 01:59:34 PM UTC 25 |
| Peak memory | 228020 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817445440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1817445440 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3761032588 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 526632181 ps |
| CPU time | 4.14 seconds |
| Started | Feb 09 01:59:40 PM UTC 25 |
| Finished | Feb 09 01:59:45 PM UTC 25 |
| Peak memory | 225756 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37610325 88 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3761032588 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1272736642 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 150780878 ps |
| CPU time | 3.25 seconds |
| Started | Feb 09 01:59:39 PM UTC 25 |
| Finished | Feb 09 01:59:43 PM UTC 25 |
| Peak memory | 225720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272736642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1272736642 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.206781850 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 53191808305 ps |
| CPU time | 180.58 seconds |
| Started | Feb 09 01:59:38 PM UTC 25 |
| Finished | Feb 09 02:02:41 PM UTC 25 |
| Peak memory | 215548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206781850 -assert nopostproc +UVM_TEST NAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_bit_bash.206781850 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3675654577 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4918604202 ps |
| CPU time | 3.53 seconds |
| Started | Feb 09 01:59:37 PM UTC 25 |
| Finished | Feb 09 01:59:41 PM UTC 25 |
| Peak memory | 215344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675654577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.3675654577 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.134244221 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 355170460 ps |
| CPU time | 1.97 seconds |
| Started | Feb 09 01:59:36 PM UTC 25 |
| Finished | Feb 09 01:59:39 PM UTC 25 |
| Peak memory | 214160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134244221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.134244221 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3731162393 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 408462678 ps |
| CPU time | 11.11 seconds |
| Started | Feb 09 01:59:40 PM UTC 25 |
| Finished | Feb 09 01:59:52 PM UTC 25 |
| Peak memory | 215600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731162393 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_csr_outstanding.3731162393 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.809422336 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 201288281 ps |
| CPU time | 5.34 seconds |
| Started | Feb 09 01:59:39 PM UTC 25 |
| Finished | Feb 09 01:59:45 PM UTC 25 |
| Peak memory | 225644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809422336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_ TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cov er_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.809422336 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4154980819 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 11127077376 ps |
| CPU time | 21.24 seconds |
| Started | Feb 09 01:59:39 PM UTC 25 |
| Finished | Feb 09 02:00:01 PM UTC 25 |
| Peak memory | 225720 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154980819 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.4154980819 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3706667111 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 232194756 ps |
| CPU time | 4.48 seconds |
| Started | Feb 09 01:59:49 PM UTC 25 |
| Finished | Feb 09 01:59:54 PM UTC 25 |
| Peak memory | 231928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37066671 11 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3706667111 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.699691992 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 164432387 ps |
| CPU time | 2.55 seconds |
| Started | Feb 09 01:59:46 PM UTC 25 |
| Finished | Feb 09 01:59:50 PM UTC 25 |
| Peak memory | 225968 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699691992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.699691992 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2304098735 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 7716096315 ps |
| CPU time | 16.98 seconds |
| Started | Feb 09 01:59:44 PM UTC 25 |
| Finished | Feb 09 02:00:03 PM UTC 25 |
| Peak memory | 215292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304098735 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_bit_bash.2304098735 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1191708420 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1836178223 ps |
| CPU time | 11.44 seconds |
| Started | Feb 09 01:59:42 PM UTC 25 |
| Finished | Feb 09 01:59:55 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191708420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.1191708420 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1351033767 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 939874116 ps |
| CPU time | 1.88 seconds |
| Started | Feb 09 01:59:41 PM UTC 25 |
| Finished | Feb 09 01:59:44 PM UTC 25 |
| Peak memory | 214100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351033767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.1351033767 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3544519043 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 452536672 ps |
| CPU time | 10.77 seconds |
| Started | Feb 09 01:59:47 PM UTC 25 |
| Finished | Feb 09 01:59:59 PM UTC 25 |
| Peak memory | 215356 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544519043 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_csr_outstanding.3544519043 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.74921210 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 205132346 ps |
| CPU time | 7.11 seconds |
| Started | Feb 09 01:59:45 PM UTC 25 |
| Finished | Feb 09 01:59:54 PM UTC 25 |
| Peak memory | 232872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74921210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_T EST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cove r_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.74921210 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2403849786 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 167878988 ps |
| CPU time | 3.24 seconds |
| Started | Feb 09 01:59:55 PM UTC 25 |
| Finished | Feb 09 01:59:59 PM UTC 25 |
| Peak memory | 229696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24038497 86 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2403849786 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.3049363635 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 229879810 ps |
| CPU time | 3.51 seconds |
| Started | Feb 09 01:59:54 PM UTC 25 |
| Finished | Feb 09 01:59:58 PM UTC 25 |
| Peak memory | 225664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049363635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3049363635 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2851303124 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 10401764065 ps |
| CPU time | 16.47 seconds |
| Started | Feb 09 01:59:53 PM UTC 25 |
| Finished | Feb 09 02:00:10 PM UTC 25 |
| Peak memory | 215540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851303124 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_bit_bash.2851303124 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1876183869 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2434608368 ps |
| CPU time | 4.94 seconds |
| Started | Feb 09 01:59:51 PM UTC 25 |
| Finished | Feb 09 01:59:57 PM UTC 25 |
| Peak memory | 215092 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876183869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.1876183869 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3787226516 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 175632985 ps |
| CPU time | 2.12 seconds |
| Started | Feb 09 01:59:51 PM UTC 25 |
| Finished | Feb 09 01:59:54 PM UTC 25 |
| Peak memory | 214780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787226516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.3787226516 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3428110015 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 529545325 ps |
| CPU time | 6.55 seconds |
| Started | Feb 09 01:59:55 PM UTC 25 |
| Finished | Feb 09 02:00:03 PM UTC 25 |
| Peak memory | 215412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428110015 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_csr_outstanding.3428110015 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3462074685 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 280639364 ps |
| CPU time | 4.09 seconds |
| Started | Feb 09 01:59:53 PM UTC 25 |
| Finished | Feb 09 01:59:58 PM UTC 25 |
| Peak memory | 225972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462074685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3462074685 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3169093413 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2050716724 ps |
| CPU time | 16.61 seconds |
| Started | Feb 09 01:59:53 PM UTC 25 |
| Finished | Feb 09 02:00:11 PM UTC 25 |
| Peak memory | 225648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169093413 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3169093413 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3756194274 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 688814583 ps |
| CPU time | 4.92 seconds |
| Started | Feb 09 02:00:00 PM UTC 25 |
| Finished | Feb 09 02:00:17 PM UTC 25 |
| Peak memory | 231840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37561942 74 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3756194274 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.2704690721 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 932143001 ps |
| CPU time | 3.14 seconds |
| Started | Feb 09 02:00:00 PM UTC 25 |
| Finished | Feb 09 02:00:15 PM UTC 25 |
| Peak memory | 225584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704690721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2704690721 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.779650464 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 13891219879 ps |
| CPU time | 51.11 seconds |
| Started | Feb 09 01:59:59 PM UTC 25 |
| Finished | Feb 09 02:00:52 PM UTC 25 |
| Peak memory | 215292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779650464 -assert nopostproc +UVM_TEST NAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_bit_bash.779650464 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2729450882 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1341011682 ps |
| CPU time | 6.26 seconds |
| Started | Feb 09 01:59:57 PM UTC 25 |
| Finished | Feb 09 02:00:05 PM UTC 25 |
| Peak memory | 215216 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729450882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.2729450882 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3770351172 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 238450047 ps |
| CPU time | 1.75 seconds |
| Started | Feb 09 01:59:56 PM UTC 25 |
| Finished | Feb 09 01:59:59 PM UTC 25 |
| Peak memory | 214100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770351172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.3770351172 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.37647770 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1788220405 ps |
| CPU time | 8.82 seconds |
| Started | Feb 09 02:00:00 PM UTC 25 |
| Finished | Feb 09 02:00:20 PM UTC 25 |
| Peak memory | 215296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37647770 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_csr_outstanding.37647770 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.4143533955 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 129831179 ps |
| CPU time | 2.67 seconds |
| Started | Feb 09 01:59:59 PM UTC 25 |
| Finished | Feb 09 02:00:03 PM UTC 25 |
| Peak memory | 225788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143533955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.4143533955 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2102548558 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1967236993 ps |
| CPU time | 14.6 seconds |
| Started | Feb 09 02:00:00 PM UTC 25 |
| Finished | Feb 09 02:00:26 PM UTC 25 |
| Peak memory | 225904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102548558 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2102548558 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1062268430 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 326573635 ps |
| CPU time | 5.76 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:20 PM UTC 25 |
| Peak memory | 229760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10622684 30 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1062268430 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3073396040 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 89194266 ps |
| CPU time | 2.35 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:16 PM UTC 25 |
| Peak memory | 225732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073396040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3073396040 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3625232021 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 6394712034 ps |
| CPU time | 17.11 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:31 PM UTC 25 |
| Peak memory | 215544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625232021 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_bit_bash.3625232021 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3637201885 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1531134569 ps |
| CPU time | 2.67 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:16 PM UTC 25 |
| Peak memory | 215160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637201885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.3637201885 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2247478884 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 273946371 ps |
| CPU time | 1.49 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:15 PM UTC 25 |
| Peak memory | 214100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247478884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.2247478884 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2618084271 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2198073727 ps |
| CPU time | 11.04 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:25 PM UTC 25 |
| Peak memory | 215484 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618084271 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_csr_outstanding.2618084271 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.1542380860 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 644941621 ps |
| CPU time | 6.1 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:20 PM UTC 25 |
| Peak memory | 225652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542380860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1542380860 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1567242678 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1411519252 ps |
| CPU time | 27.17 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:41 PM UTC 25 |
| Peak memory | 225600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567242678 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1567242678 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.582292923 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 124945360 ps |
| CPU time | 3.64 seconds |
| Started | Feb 09 02:00:20 PM UTC 25 |
| Finished | Feb 09 02:00:25 PM UTC 25 |
| Peak memory | 229640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58229292 3 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.582292923 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3869991767 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 93395364 ps |
| CPU time | 2.15 seconds |
| Started | Feb 09 02:00:17 PM UTC 25 |
| Finished | Feb 09 02:00:20 PM UTC 25 |
| Peak memory | 225904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869991767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3869991767 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1519726663 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 3514838417 ps |
| CPU time | 20.26 seconds |
| Started | Feb 09 02:00:16 PM UTC 25 |
| Finished | Feb 09 02:00:38 PM UTC 25 |
| Peak memory | 215288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519726663 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_bit_bash.1519726663 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1350739127 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 6207447445 ps |
| CPU time | 16.04 seconds |
| Started | Feb 09 02:00:15 PM UTC 25 |
| Finished | Feb 09 02:00:32 PM UTC 25 |
| Peak memory | 215608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350739127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.1350739127 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3942582894 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 693718816 ps |
| CPU time | 4.93 seconds |
| Started | Feb 09 02:00:13 PM UTC 25 |
| Finished | Feb 09 02:00:19 PM UTC 25 |
| Peak memory | 214768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942582894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.3942582894 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1824807567 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 597301554 ps |
| CPU time | 5.37 seconds |
| Started | Feb 09 02:00:18 PM UTC 25 |
| Finished | Feb 09 02:00:25 PM UTC 25 |
| Peak memory | 215740 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824807567 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_csr_outstanding.1824807567 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.121919193 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 203929880 ps |
| CPU time | 5.87 seconds |
| Started | Feb 09 02:00:16 PM UTC 25 |
| Finished | Feb 09 02:00:23 PM UTC 25 |
| Peak memory | 225708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121919193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_ TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cov er_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.121919193 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4205627900 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 313333207 ps |
| CPU time | 3.28 seconds |
| Started | Feb 09 02:00:26 PM UTC 25 |
| Finished | Feb 09 02:00:30 PM UTC 25 |
| Peak memory | 230136 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42056279 00 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4205627900 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2527171675 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 157618521 ps |
| CPU time | 3.1 seconds |
| Started | Feb 09 02:00:23 PM UTC 25 |
| Finished | Feb 09 02:00:28 PM UTC 25 |
| Peak memory | 225592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527171675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2527171675 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2840934302 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 4216791854 ps |
| CPU time | 6.04 seconds |
| Started | Feb 09 02:00:21 PM UTC 25 |
| Finished | Feb 09 02:00:29 PM UTC 25 |
| Peak memory | 215344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840934302 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_bit_bash.2840934302 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3757357248 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3556977509 ps |
| CPU time | 4.29 seconds |
| Started | Feb 09 02:00:21 PM UTC 25 |
| Finished | Feb 09 02:00:27 PM UTC 25 |
| Peak memory | 215544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757357248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.3757357248 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.592172756 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 182534659 ps |
| CPU time | 1.22 seconds |
| Started | Feb 09 02:00:20 PM UTC 25 |
| Finished | Feb 09 02:00:23 PM UTC 25 |
| Peak memory | 214160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592172756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.592172756 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2128236340 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 194093447 ps |
| CPU time | 5.71 seconds |
| Started | Feb 09 02:00:26 PM UTC 25 |
| Finished | Feb 09 02:00:32 PM UTC 25 |
| Peak memory | 215364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128236340 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_csr_outstanding.2128236340 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_errors.179619183 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 280913283 ps |
| CPU time | 3.5 seconds |
| Started | Feb 09 02:00:21 PM UTC 25 |
| Finished | Feb 09 02:00:26 PM UTC 25 |
| Peak memory | 225708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179619183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_ TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cov er_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.179619183 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2300136536 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2769449137 ps |
| CPU time | 21.09 seconds |
| Started | Feb 09 02:00:23 PM UTC 25 |
| Finished | Feb 09 02:00:46 PM UTC 25 |
| Peak memory | 226032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300136536 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2300136536 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2180876032 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 179837390 ps |
| CPU time | 5.75 seconds |
| Started | Feb 09 02:00:31 PM UTC 25 |
| Finished | Feb 09 02:00:38 PM UTC 25 |
| Peak memory | 231864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21808760 32 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2180876032 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_csr_rw.609008093 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 97955596 ps |
| CPU time | 3.5 seconds |
| Started | Feb 09 02:00:29 PM UTC 25 |
| Finished | Feb 09 02:00:34 PM UTC 25 |
| Peak memory | 225744 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609008093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.609008093 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.977810650 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2932303568 ps |
| CPU time | 5.94 seconds |
| Started | Feb 09 02:00:27 PM UTC 25 |
| Finished | Feb 09 02:00:34 PM UTC 25 |
| Peak memory | 215292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977810650 -assert nopostproc +UVM_TEST NAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_bit_bash.977810650 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1521113392 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 7418987015 ps |
| CPU time | 21.22 seconds |
| Started | Feb 09 02:00:27 PM UTC 25 |
| Finished | Feb 09 02:00:50 PM UTC 25 |
| Peak memory | 215600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521113392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.1521113392 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2018820326 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 250865239 ps |
| CPU time | 1.19 seconds |
| Started | Feb 09 02:00:26 PM UTC 25 |
| Finished | Feb 09 02:00:28 PM UTC 25 |
| Peak memory | 214100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018820326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.2018820326 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.934157105 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 318802468 ps |
| CPU time | 9.61 seconds |
| Started | Feb 09 02:00:30 PM UTC 25 |
| Finished | Feb 09 02:00:41 PM UTC 25 |
| Peak memory | 215736 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934157105 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr_outstanding.934157105 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.2804579930 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 464092704 ps |
| CPU time | 7.48 seconds |
| Started | Feb 09 02:00:28 PM UTC 25 |
| Finished | Feb 09 02:00:36 PM UTC 25 |
| Peak memory | 225652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804579930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2804579930 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2738294247 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 8544287465 ps |
| CPU time | 25.69 seconds |
| Started | Feb 09 02:00:29 PM UTC 25 |
| Finished | Feb 09 02:00:56 PM UTC 25 |
| Peak memory | 226076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738294247 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2738294247 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1062760864 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 342032856 ps |
| CPU time | 3.55 seconds |
| Started | Feb 09 02:00:35 PM UTC 25 |
| Finished | Feb 09 02:00:40 PM UTC 25 |
| Peak memory | 225600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10627608 64 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1062760864 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.2806618563 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 150525508 ps |
| CPU time | 3.26 seconds |
| Started | Feb 09 02:00:34 PM UTC 25 |
| Finished | Feb 09 02:00:39 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806618563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2806618563 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.759109996 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 10504993481 ps |
| CPU time | 39.95 seconds |
| Started | Feb 09 02:00:32 PM UTC 25 |
| Finished | Feb 09 02:01:14 PM UTC 25 |
| Peak memory | 215292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759109996 -assert nopostproc +UVM_TEST NAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_bit_bash.759109996 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.425165165 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4324959268 ps |
| CPU time | 5.3 seconds |
| Started | Feb 09 02:00:31 PM UTC 25 |
| Finished | Feb 09 02:00:38 PM UTC 25 |
| Peak memory | 215272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425165165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.425165165 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4106025181 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 547558459 ps |
| CPU time | 2.69 seconds |
| Started | Feb 09 02:00:31 PM UTC 25 |
| Finished | Feb 09 02:00:35 PM UTC 25 |
| Peak memory | 214944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106025181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.4106025181 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3579300476 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 672221414 ps |
| CPU time | 6.5 seconds |
| Started | Feb 09 02:00:35 PM UTC 25 |
| Finished | Feb 09 02:00:43 PM UTC 25 |
| Peak memory | 215476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579300476 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_csr_outstanding.3579300476 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3021717802 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1380533700 ps |
| CPU time | 10.33 seconds |
| Started | Feb 09 02:00:33 PM UTC 25 |
| Finished | Feb 09 02:00:45 PM UTC 25 |
| Peak memory | 225512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021717802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3021717802 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.832486433 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2250113159 ps |
| CPU time | 25.66 seconds |
| Started | Feb 09 02:00:33 PM UTC 25 |
| Finished | Feb 09 02:01:00 PM UTC 25 |
| Peak memory | 225788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832486433 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.832486433 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2593500587 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 21994110939 ps |
| CPU time | 95.91 seconds |
| Started | Feb 09 01:57:17 PM UTC 25 |
| Finished | Feb 09 01:58:55 PM UTC 25 |
| Peak memory | 225784 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593500587 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_aliasing.2593500587 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3507564888 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1442613515 ps |
| CPU time | 67.42 seconds |
| Started | Feb 09 01:57:32 PM UTC 25 |
| Finished | Feb 09 01:58:41 PM UTC 25 |
| Peak memory | 225848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507564888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3507564888 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3505085710 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 135272927 ps |
| CPU time | 3.97 seconds |
| Started | Feb 09 01:57:31 PM UTC 25 |
| Finished | Feb 09 01:57:37 PM UTC 25 |
| Peak memory | 225904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505085710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3505085710 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.972867023 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 409593454 ps |
| CPU time | 4.34 seconds |
| Started | Feb 09 01:57:34 PM UTC 25 |
| Finished | Feb 09 01:57:39 PM UTC 25 |
| Peak memory | 232056 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97286702 3 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.972867023 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2013818146 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 149098848 ps |
| CPU time | 3.94 seconds |
| Started | Feb 09 01:57:32 PM UTC 25 |
| Finished | Feb 09 01:57:37 PM UTC 25 |
| Peak memory | 225648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013818146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2013818146 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2372129199 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 15309756689 ps |
| CPU time | 51.91 seconds |
| Started | Feb 09 01:57:25 PM UTC 25 |
| Finished | Feb 09 01:58:19 PM UTC 25 |
| Peak memory | 215288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372129199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_aliasing.2372129199 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.640018527 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 40391551 ps |
| CPU time | 1.23 seconds |
| Started | Feb 09 01:57:25 PM UTC 25 |
| Finished | Feb 09 01:57:28 PM UTC 25 |
| Peak memory | 214100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640018527 -assert nopostproc +UVM_TEST NAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.640018527 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2936981424 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1909286491 ps |
| CPU time | 12.89 seconds |
| Started | Feb 09 01:57:24 PM UTC 25 |
| Finished | Feb 09 01:57:38 PM UTC 25 |
| Peak memory | 215600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936981424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_hw_reset.2936981424 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.903859720 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 10970865085 ps |
| CPU time | 26.55 seconds |
| Started | Feb 09 01:57:24 PM UTC 25 |
| Finished | Feb 09 01:57:52 PM UTC 25 |
| Peak memory | 215220 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903859720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.903859720 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2541152633 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 498562451 ps |
| CPU time | 2.59 seconds |
| Started | Feb 09 01:57:23 PM UTC 25 |
| Finished | Feb 09 01:57:27 PM UTC 25 |
| Peak memory | 215008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541152633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_aliasing.2541152633 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2601495326 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 38881179498 ps |
| CPU time | 187.09 seconds |
| Started | Feb 09 01:57:20 PM UTC 25 |
| Finished | Feb 09 02:00:30 PM UTC 25 |
| Peak memory | 215288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601495326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_bit_bash.2601495326 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3463834302 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 607382180 ps |
| CPU time | 4.6 seconds |
| Started | Feb 09 01:57:17 PM UTC 25 |
| Finished | Feb 09 01:57:23 PM UTC 25 |
| Peak memory | 215324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463834302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_hw_reset.3463834302 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2285941678 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 254010066 ps |
| CPU time | 1.61 seconds |
| Started | Feb 09 01:57:20 PM UTC 25 |
| Finished | Feb 09 01:57:23 PM UTC 25 |
| Peak memory | 214168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285941678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2285941678 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_partial_access.815918599 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 39092611 ps |
| CPU time | 1.09 seconds |
| Started | Feb 09 01:57:30 PM UTC 25 |
| Finished | Feb 09 01:57:33 PM UTC 25 |
| Peak memory | 214164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815918599 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_partial_access.815918599 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_mem_walk.3257769524 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 129687803 ps |
| CPU time | 1.09 seconds |
| Started | Feb 09 01:57:28 PM UTC 25 |
| Finished | Feb 09 01:57:31 PM UTC 25 |
| Peak memory | 214104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257769524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3257769524 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4250256359 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 557649507 ps |
| CPU time | 6.99 seconds |
| Started | Feb 09 01:57:34 PM UTC 25 |
| Finished | Feb 09 01:57:42 PM UTC 25 |
| Peak memory | 215664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250256359 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_csr_outstanding.4250256359 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1585600206 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 76069014575 ps |
| CPU time | 49.77 seconds |
| Started | Feb 09 01:57:26 PM UTC 25 |
| Finished | Feb 09 01:58:18 PM UTC 25 |
| Peak memory | 232772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158560 0206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1585600206 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_errors.517788381 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 498665095 ps |
| CPU time | 7.29 seconds |
| Started | Feb 09 01:57:27 PM UTC 25 |
| Finished | Feb 09 01:57:36 PM UTC 25 |
| Peak memory | 225852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517788381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_ TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cov er_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.517788381 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4154409488 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1261556013 ps |
| CPU time | 23.85 seconds |
| Started | Feb 09 01:57:28 PM UTC 25 |
| Finished | Feb 09 01:57:54 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154409488 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.4154409488 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2451357819 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 6946571551 ps |
| CPU time | 92.79 seconds |
| Started | Feb 09 01:57:36 PM UTC 25 |
| Finished | Feb 09 01:59:11 PM UTC 25 |
| Peak memory | 225912 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451357819 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_aliasing.2451357819 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3184476102 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 14949731207 ps |
| CPU time | 95.25 seconds |
| Started | Feb 09 01:57:59 PM UTC 25 |
| Finished | Feb 09 01:59:36 PM UTC 25 |
| Peak memory | 225840 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184476102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3184476102 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2280059329 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1104124262 ps |
| CPU time | 3.85 seconds |
| Started | Feb 09 01:57:57 PM UTC 25 |
| Finished | Feb 09 01:58:02 PM UTC 25 |
| Peak memory | 225904 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280059329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2280059329 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3997710241 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 176729668 ps |
| CPU time | 3.28 seconds |
| Started | Feb 09 01:58:00 PM UTC 25 |
| Finished | Feb 09 01:58:04 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39977102 41 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3997710241 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_csr_rw.1281681130 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 205410934 ps |
| CPU time | 3.96 seconds |
| Started | Feb 09 01:57:58 PM UTC 25 |
| Finished | Feb 09 01:58:03 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281681130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1281681130 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3717683263 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 202620169296 ps |
| CPU time | 418.77 seconds |
| Started | Feb 09 01:57:42 PM UTC 25 |
| Finished | Feb 09 02:04:47 PM UTC 25 |
| Peak memory | 219384 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717683263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_aliasing.3717683263 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1530301980 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 85068850601 ps |
| CPU time | 96.99 seconds |
| Started | Feb 09 01:57:40 PM UTC 25 |
| Finished | Feb 09 01:59:19 PM UTC 25 |
| Peak memory | 215540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530301980 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.1530301980 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.354146296 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 4898981811 ps |
| CPU time | 15.23 seconds |
| Started | Feb 09 01:57:39 PM UTC 25 |
| Finished | Feb 09 01:57:56 PM UTC 25 |
| Peak memory | 215796 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354146296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_hw_reset.354146296 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.335626962 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 2484830869 ps |
| CPU time | 16.3 seconds |
| Started | Feb 09 01:57:40 PM UTC 25 |
| Finished | Feb 09 01:57:58 PM UTC 25 |
| Peak memory | 215284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335626962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.335626962 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4249757111 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 960063533 ps |
| CPU time | 6.55 seconds |
| Started | Feb 09 01:57:38 PM UTC 25 |
| Finished | Feb 09 01:57:46 PM UTC 25 |
| Peak memory | 214412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249757111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_aliasing.4249757111 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2764940908 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5218389506 ps |
| CPU time | 18.34 seconds |
| Started | Feb 09 01:57:38 PM UTC 25 |
| Finished | Feb 09 01:57:58 PM UTC 25 |
| Peak memory | 214820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764940908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_bit_bash.2764940908 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.101143705 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1428558343 ps |
| CPU time | 3.51 seconds |
| Started | Feb 09 01:57:37 PM UTC 25 |
| Finished | Feb 09 01:57:42 PM UTC 25 |
| Peak memory | 214940 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101143705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_hw_reset.101143705 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.220770055 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 476433168 ps |
| CPU time | 1.61 seconds |
| Started | Feb 09 01:57:37 PM UTC 25 |
| Finished | Feb 09 01:57:40 PM UTC 25 |
| Peak memory | 214100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220770055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.220770055 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_partial_access.640646036 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 100733177 ps |
| CPU time | 1.24 seconds |
| Started | Feb 09 01:57:56 PM UTC 25 |
| Finished | Feb 09 01:57:59 PM UTC 25 |
| Peak memory | 214164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640646036 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_partial_access.640646036 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_mem_walk.1524678611 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 52500812 ps |
| CPU time | 1.33 seconds |
| Started | Feb 09 01:57:54 PM UTC 25 |
| Finished | Feb 09 01:57:57 PM UTC 25 |
| Peak memory | 214104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524678611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1524678611 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3710428215 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 495085625 ps |
| CPU time | 5.49 seconds |
| Started | Feb 09 01:57:59 PM UTC 25 |
| Finished | Feb 09 01:58:06 PM UTC 25 |
| Peak memory | 215732 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710428215 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_outstanding.3710428215 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2795386043 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 66880368237 ps |
| CPU time | 164.38 seconds |
| Started | Feb 09 01:57:42 PM UTC 25 |
| Finished | Feb 09 02:00:29 PM UTC 25 |
| Peak memory | 243320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279538 6043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2795386043 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_errors.1109414101 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2493790803 ps |
| CPU time | 8.51 seconds |
| Started | Feb 09 01:57:46 PM UTC 25 |
| Finished | Feb 09 01:57:56 PM UTC 25 |
| Peak memory | 225836 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109414101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1109414101 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/3.rv_dm_tl_intg_err.412816078 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 5766827167 ps |
| CPU time | 25.14 seconds |
| Started | Feb 09 01:57:52 PM UTC 25 |
| Finished | Feb 09 01:58:19 PM UTC 25 |
| Peak memory | 226100 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412816078 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.412816078 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2944614568 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 860282550 ps |
| CPU time | 37.38 seconds |
| Started | Feb 09 01:58:02 PM UTC 25 |
| Finished | Feb 09 01:58:41 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944614568 -assert nopostp roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_aliasing.2944614568 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3269136703 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 7649907580 ps |
| CPU time | 41.69 seconds |
| Started | Feb 09 01:58:20 PM UTC 25 |
| Finished | Feb 09 01:59:03 PM UTC 25 |
| Peak memory | 215536 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269136703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3269136703 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3019093302 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 567907929 ps |
| CPU time | 4.12 seconds |
| Started | Feb 09 01:58:19 PM UTC 25 |
| Finished | Feb 09 01:58:24 PM UTC 25 |
| Peak memory | 225648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019093302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3019093302 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.935466237 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 370067664 ps |
| CPU time | 7.07 seconds |
| Started | Feb 09 01:58:22 PM UTC 25 |
| Finished | Feb 09 01:58:30 PM UTC 25 |
| Peak memory | 232952 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93546623 7 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.935466237 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_csr_rw.4238827148 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 950700368 ps |
| CPU time | 2.48 seconds |
| Started | Feb 09 01:58:20 PM UTC 25 |
| Finished | Feb 09 01:58:23 PM UTC 25 |
| Peak memory | 225648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238827148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4238827148 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1762837539 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 204915067753 ps |
| CPU time | 393.08 seconds |
| Started | Feb 09 01:58:10 PM UTC 25 |
| Finished | Feb 09 02:04:49 PM UTC 25 |
| Peak memory | 219640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762837539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_aliasing.1762837539 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.718970947 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 13482428545 ps |
| CPU time | 7.96 seconds |
| Started | Feb 09 01:58:08 PM UTC 25 |
| Finished | Feb 09 01:58:17 PM UTC 25 |
| Peak memory | 215540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718970947 -assert nopostproc +UVM_TEST NAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.718970947 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2121208913 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3594409712 ps |
| CPU time | 21.57 seconds |
| Started | Feb 09 01:58:06 PM UTC 25 |
| Finished | Feb 09 01:58:29 PM UTC 25 |
| Peak memory | 215420 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121208913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_hw_reset.2121208913 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1975639994 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2118859999 ps |
| CPU time | 8.2 seconds |
| Started | Feb 09 01:58:07 PM UTC 25 |
| Finished | Feb 09 01:58:17 PM UTC 25 |
| Peak memory | 215156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975639994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1975639994 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.649130974 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1384094537 ps |
| CPU time | 3.35 seconds |
| Started | Feb 09 01:58:05 PM UTC 25 |
| Finished | Feb 09 01:58:10 PM UTC 25 |
| Peak memory | 214944 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649130974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_aliasing.649130974 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2974339775 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3997433075 ps |
| CPU time | 3.81 seconds |
| Started | Feb 09 01:58:05 PM UTC 25 |
| Finished | Feb 09 01:58:10 PM UTC 25 |
| Peak memory | 215224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974339775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_bit_bash.2974339775 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2477369596 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 472872701 ps |
| CPU time | 1.82 seconds |
| Started | Feb 09 01:58:03 PM UTC 25 |
| Finished | Feb 09 01:58:06 PM UTC 25 |
| Peak memory | 214224 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477369596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_ test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim- vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_hw_reset.2477369596 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2774454229 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 248895951 ps |
| CPU time | 1.63 seconds |
| Started | Feb 09 01:58:04 PM UTC 25 |
| Finished | Feb 09 01:58:07 PM UTC 25 |
| Peak memory | 214168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774454229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2774454229 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3308063683 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 59253506 ps |
| CPU time | 1.3 seconds |
| Started | Feb 09 01:58:18 PM UTC 25 |
| Finished | Feb 09 01:58:21 PM UTC 25 |
| Peak memory | 214160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308063683 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm- sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_partial_access.3308063683 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_mem_walk.585590558 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 71192511 ps |
| CPU time | 1.07 seconds |
| Started | Feb 09 01:58:17 PM UTC 25 |
| Finished | Feb 09 01:58:20 PM UTC 25 |
| Peak memory | 214164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585590558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.585590558 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3321913048 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 251629512 ps |
| CPU time | 6.07 seconds |
| Started | Feb 09 01:58:21 PM UTC 25 |
| Finished | Feb 09 01:58:28 PM UTC 25 |
| Peak memory | 215476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321913048 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_csr_outstanding.3321913048 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2961982491 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 24764307587 ps |
| CPU time | 68.26 seconds |
| Started | Feb 09 01:58:11 PM UTC 25 |
| Finished | Feb 09 01:59:22 PM UTC 25 |
| Peak memory | 232772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296198 2491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2961982491 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_errors.1864596518 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 183474811 ps |
| CPU time | 3.3 seconds |
| Started | Feb 09 01:58:11 PM UTC 25 |
| Finished | Feb 09 01:58:16 PM UTC 25 |
| Peak memory | 227668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864596518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1864596518 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tl_intg_err.549630397 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4632136256 ps |
| CPU time | 11.16 seconds |
| Started | Feb 09 01:58:16 PM UTC 25 |
| Finished | Feb 09 01:58:29 PM UTC 25 |
| Peak memory | 225780 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549630397 -assert nopostproc +UVM_TESTNAME=rv_dm_bas e_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.549630397 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2829248107 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1985249653 ps |
| CPU time | 6.1 seconds |
| Started | Feb 09 01:58:31 PM UTC 25 |
| Finished | Feb 09 01:58:38 PM UTC 25 |
| Peak memory | 231864 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28292481 07 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2829248107 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_csr_rw.3203582005 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 59044739 ps |
| CPU time | 2.24 seconds |
| Started | Feb 09 01:58:30 PM UTC 25 |
| Finished | Feb 09 01:58:34 PM UTC 25 |
| Peak memory | 225848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203582005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3203582005 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2948226838 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 87867624 ps |
| CPU time | 1.51 seconds |
| Started | Feb 09 01:58:26 PM UTC 25 |
| Finished | Feb 09 01:58:29 PM UTC 25 |
| Peak memory | 214164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948226838 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_bit_bash.2948226838 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.190383521 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 9292456993 ps |
| CPU time | 48.86 seconds |
| Started | Feb 09 01:58:25 PM UTC 25 |
| Finished | Feb 09 01:59:16 PM UTC 25 |
| Peak memory | 215468 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190383521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.190383521 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4103816525 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 98814093 ps |
| CPU time | 1.51 seconds |
| Started | Feb 09 01:58:25 PM UTC 25 |
| Finished | Feb 09 01:58:28 PM UTC 25 |
| Peak memory | 214096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103816525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.4103816525 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.284509520 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 590397210 ps |
| CPU time | 9.19 seconds |
| Started | Feb 09 01:58:30 PM UTC 25 |
| Finished | Feb 09 01:58:41 PM UTC 25 |
| Peak memory | 215616 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284509520 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_csr_outstanding.284509520 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2588834017 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 48845416364 ps |
| CPU time | 201.98 seconds |
| Started | Feb 09 01:58:28 PM UTC 25 |
| Finished | Feb 09 02:01:53 PM UTC 25 |
| Peak memory | 232772 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258883 4017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2588834017 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_errors.3864991042 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 234315637 ps |
| CPU time | 4.52 seconds |
| Started | Feb 09 01:58:29 PM UTC 25 |
| Finished | Feb 09 01:58:35 PM UTC 25 |
| Peak memory | 225708 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864991042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3864991042 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3711664678 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1675398015 ps |
| CPU time | 17.37 seconds |
| Started | Feb 09 01:58:30 PM UTC 25 |
| Finished | Feb 09 01:58:49 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711664678 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3711664678 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1017685323 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 568557569 ps |
| CPU time | 6.88 seconds |
| Started | Feb 09 01:58:46 PM UTC 25 |
| Finished | Feb 09 01:58:54 PM UTC 25 |
| Peak memory | 231792 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10176853 23 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1017685323 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_csr_rw.272679159 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 141250589 ps |
| CPU time | 1.65 seconds |
| Started | Feb 09 01:58:42 PM UTC 25 |
| Finished | Feb 09 01:58:44 PM UTC 25 |
| Peak memory | 224156 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272679159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/ cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.272679159 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2895425243 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 12066551058 ps |
| CPU time | 7.61 seconds |
| Started | Feb 09 01:58:38 PM UTC 25 |
| Finished | Feb 09 01:58:47 PM UTC 25 |
| Peak memory | 215284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895425243 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_bit_bash.2895425243 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.693087385 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1931447998 ps |
| CPU time | 6.85 seconds |
| Started | Feb 09 01:58:35 PM UTC 25 |
| Finished | Feb 09 01:58:43 PM UTC 25 |
| Peak memory | 215212 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693087385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.693087385 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3970606924 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 239508054 ps |
| CPU time | 2.62 seconds |
| Started | Feb 09 01:58:34 PM UTC 25 |
| Finished | Feb 09 01:58:38 PM UTC 25 |
| Peak memory | 215196 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970606924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3970606924 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1487736579 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 251425813 ps |
| CPU time | 5.73 seconds |
| Started | Feb 09 01:58:45 PM UTC 25 |
| Finished | Feb 09 01:58:52 PM UTC 25 |
| Peak memory | 215408 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487736579 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_d m-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_csr_outstanding.1487736579 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.506021347 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 23298769402 ps |
| CPU time | 92.39 seconds |
| Started | Feb 09 01:58:39 PM UTC 25 |
| Finished | Feb 09 02:00:14 PM UTC 25 |
| Peak memory | 232972 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506021 347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.506021347 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_errors.2785042084 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 673273998 ps |
| CPU time | 5.72 seconds |
| Started | Feb 09 01:58:41 PM UTC 25 |
| Finished | Feb 09 01:58:48 PM UTC 25 |
| Peak memory | 225644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785042084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2785042084 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1278518949 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2789156760 ps |
| CPU time | 23.35 seconds |
| Started | Feb 09 01:58:42 PM UTC 25 |
| Finished | Feb 09 01:59:06 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278518949 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1278518949 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1119713665 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 240018230 ps |
| CPU time | 3.87 seconds |
| Started | Feb 09 01:58:59 PM UTC 25 |
| Finished | Feb 09 01:59:04 PM UTC 25 |
| Peak memory | 232696 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11197136 65 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1119713665 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_csr_rw.1230861543 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 39694768 ps |
| CPU time | 2.23 seconds |
| Started | Feb 09 01:58:55 PM UTC 25 |
| Finished | Feb 09 01:58:58 PM UTC 25 |
| Peak memory | 225524 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230861543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1230861543 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2067289957 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 24463172389 ps |
| CPU time | 32.21 seconds |
| Started | Feb 09 01:58:50 PM UTC 25 |
| Finished | Feb 09 01:59:24 PM UTC 25 |
| Peak memory | 215284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067289957 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_bit_bash.2067289957 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2510200571 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2859956039 ps |
| CPU time | 4.34 seconds |
| Started | Feb 09 01:58:49 PM UTC 25 |
| Finished | Feb 09 01:58:54 PM UTC 25 |
| Peak memory | 215340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510200571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2510200571 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.514255130 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 212735121 ps |
| CPU time | 1.36 seconds |
| Started | Feb 09 01:58:48 PM UTC 25 |
| Finished | Feb 09 01:58:50 PM UTC 25 |
| Peak memory | 214160 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514255130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.514255130 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.706814053 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 282134424 ps |
| CPU time | 6.27 seconds |
| Started | Feb 09 01:58:56 PM UTC 25 |
| Finished | Feb 09 01:59:04 PM UTC 25 |
| Peak memory | 215672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706814053 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_csr_outstanding.706814053 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3126203543 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 58383562918 ps |
| CPU time | 375.51 seconds |
| Started | Feb 09 01:58:51 PM UTC 25 |
| Finished | Feb 09 02:05:11 PM UTC 25 |
| Peak memory | 232692 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312620 3543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3126203543 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_errors.2103565770 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 221097409 ps |
| CPU time | 8.53 seconds |
| Started | Feb 09 01:58:53 PM UTC 25 |
| Finished | Feb 09 01:59:03 PM UTC 25 |
| Peak memory | 225588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103565770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2103565770 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2812913997 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 5927576350 ps |
| CPU time | 41.57 seconds |
| Started | Feb 09 01:58:55 PM UTC 25 |
| Finished | Feb 09 01:59:38 PM UTC 25 |
| Peak memory | 232324 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812913997 -assert nopostproc +UVM_TESTNAME=rv_dm_ba se_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2812913997 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1784165377 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 222442035 ps |
| CPU time | 2.4 seconds |
| Started | Feb 09 01:59:16 PM UTC 25 |
| Finished | Feb 09 01:59:19 PM UTC 25 |
| Peak memory | 232476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17841653 77 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1784165377 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_csr_rw.2894194322 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 82288808 ps |
| CPU time | 2.45 seconds |
| Started | Feb 09 01:59:12 PM UTC 25 |
| Finished | Feb 09 01:59:15 PM UTC 25 |
| Peak memory | 225848 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894194322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2894194322 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.198417940 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 24067222052 ps |
| CPU time | 41.97 seconds |
| Started | Feb 09 01:59:04 PM UTC 25 |
| Finished | Feb 09 01:59:48 PM UTC 25 |
| Peak memory | 215284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198417940 -assert nopostproc +UVM_TEST NAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_bit_bash.198417940 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2186238994 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3204097607 ps |
| CPU time | 10.95 seconds |
| Started | Feb 09 01:59:04 PM UTC 25 |
| Finished | Feb 09 01:59:16 PM UTC 25 |
| Peak memory | 215284 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186238994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2186238994 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2448134867 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 287377481 ps |
| CPU time | 1.34 seconds |
| Started | Feb 09 01:59:03 PM UTC 25 |
| Finished | Feb 09 01:59:06 PM UTC 25 |
| Peak memory | 214168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448134867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2448134867 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.104838994 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 305355411 ps |
| CPU time | 9.72 seconds |
| Started | Feb 09 01:59:16 PM UTC 25 |
| Finished | Feb 09 01:59:27 PM UTC 25 |
| Peak memory | 215424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104838994 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr_outstanding.104838994 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.476763827 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 20440922354 ps |
| CPU time | 44.8 seconds |
| Started | Feb 09 01:59:05 PM UTC 25 |
| Finished | Feb 09 01:59:52 PM UTC 25 |
| Peak memory | 232764 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476763 827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.476763827 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_errors.1265944635 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 496324141 ps |
| CPU time | 7.57 seconds |
| Started | Feb 09 01:59:06 PM UTC 25 |
| Finished | Feb 09 01:59:15 PM UTC 25 |
| Peak memory | 225556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265944635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1265944635 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/8.rv_dm_tl_intg_err.68154360 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1695821649 ps |
| CPU time | 12.78 seconds |
| Started | Feb 09 01:59:08 PM UTC 25 |
| Finished | Feb 09 01:59:22 PM UTC 25 |
| Peak memory | 232820 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68154360 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/c overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.68154360 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3357204822 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 182925732 ps |
| CPU time | 3.66 seconds |
| Started | Feb 09 01:59:24 PM UTC 25 |
| Finished | Feb 09 01:59:29 PM UTC 25 |
| Peak memory | 225656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33572048 22 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3357204822 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_rw.3821794603 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 519042215 ps |
| CPU time | 3.73 seconds |
| Started | Feb 09 01:59:22 PM UTC 25 |
| Finished | Feb 09 01:59:27 PM UTC 25 |
| Peak memory | 225672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821794603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3821794603 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1526685973 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 6976767464 ps |
| CPU time | 3.25 seconds |
| Started | Feb 09 01:59:20 PM UTC 25 |
| Finished | Feb 09 01:59:24 PM UTC 25 |
| Peak memory | 215292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526685973 -assert nopostproc +UVM_TES TNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_bit_bash.1526685973 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.52901323 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 10249953412 ps |
| CPU time | 19.68 seconds |
| Started | Feb 09 01:59:17 PM UTC 25 |
| Finished | Feb 09 01:59:38 PM UTC 25 |
| Peak memory | 215288 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52901323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.52901323 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1894304351 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 330234420 ps |
| CPU time | 1.68 seconds |
| Started | Feb 09 01:59:17 PM UTC 25 |
| Finished | Feb 09 01:59:20 PM UTC 25 |
| Peak memory | 214124 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894304351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/co verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1894304351 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.907997812 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 576681781 ps |
| CPU time | 9.7 seconds |
| Started | Feb 09 01:59:22 PM UTC 25 |
| Finished | Feb 09 01:59:33 PM UTC 25 |
| Peak memory | 215172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907997812 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_csr_outstanding.907997812 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2334883432 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 25861556517 ps |
| CPU time | 37.72 seconds |
| Started | Feb 09 01:59:20 PM UTC 25 |
| Finished | Feb 09 01:59:59 PM UTC 25 |
| Peak memory | 227844 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233488 3432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2334883432 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_errors.2833995753 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 295951938 ps |
| CPU time | 6.21 seconds |
| Started | Feb 09 01:59:20 PM UTC 25 |
| Finished | Feb 09 01:59:27 PM UTC 25 |
| Peak memory | 232592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833995753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM _TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/co ver_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2833995753 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_tl_intg_err.54070415 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 967324452 ps |
| CPU time | 16.78 seconds |
| Started | Feb 09 01:59:21 PM UTC 25 |
| Finished | Feb 09 01:59:39 PM UTC 25 |
| Peak memory | 225644 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54070415 -assert nopostproc +UVM_TESTNAME=rv_dm_base _test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/c overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.54070415 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.1957687897 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2783292447 ps |
| CPU time | 6.41 seconds |
| Started | Feb 09 02:00:41 PM UTC 25 |
| Finished | Feb 09 02:00:48 PM UTC 25 |
| Peak memory | 216272 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957687897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1957687897 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.2323807387 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 934276066 ps |
| CPU time | 6 seconds |
| Started | Feb 09 02:00:42 PM UTC 25 |
| Finished | Feb 09 02:00:49 PM UTC 25 |
| Peak memory | 215704 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323807387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmder r_busy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.rv_dm_cmderr_busy.2323807387 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_cmderr_busy/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1882662302 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 280826941 ps |
| CPU time | 1.91 seconds |
| Started | Feb 09 02:00:47 PM UTC 25 |
| Finished | Feb 09 02:00:50 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882662302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataa ddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1882662302 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3217561356 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 117244982 ps |
| CPU time | 1.43 seconds |
| Started | Feb 09 02:00:53 PM UTC 25 |
| Finished | Feb 09 02:00:55 PM UTC 25 |
| Peak memory | 237296 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217561356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug _disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 0.rv_dm_debug_disabled.3217561356 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2039586841 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 5098195096 ps |
| CPU time | 21.44 seconds |
| Started | Feb 09 02:00:39 PM UTC 25 |
| Finished | Feb 09 02:01:01 PM UTC 25 |
| Peak memory | 216204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039586841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl_access.2039586841 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1009555032 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 545124266 ps |
| CPU time | 2.13 seconds |
| Started | Feb 09 02:00:50 PM UTC 25 |
| Finished | Feb 09 02:00:54 PM UTC 25 |
| Peak memory | 215760 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009555032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_ dmi_debug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1009555032 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1738851634 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1052494536 ps |
| CPU time | 6.47 seconds |
| Started | Feb 09 02:00:50 PM UTC 25 |
| Finished | Feb 09 02:00:58 PM UTC 25 |
| Peak memory | 215640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738851634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_ dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1738851634 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3276590068 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 127511798 ps |
| CPU time | 1.65 seconds |
| Started | Feb 09 02:00:50 PM UTC 25 |
| Finished | Feb 09 02:00:53 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276590068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_ dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3276590068 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.2520394381 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 91977387 ps |
| CPU time | 1.47 seconds |
| Started | Feb 09 02:00:44 PM UTC 25 |
| Finished | Feb 09 02:00:47 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520394381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_t l_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2520394381 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2770777877 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 763663615 ps |
| CPU time | 5.87 seconds |
| Started | Feb 09 02:00:45 PM UTC 25 |
| Finished | Feb 09 02:00:52 PM UTC 25 |
| Peak memory | 216068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770777877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_t l_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2770777877 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.162907085 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 979778322 ps |
| CPU time | 1.65 seconds |
| Started | Feb 09 02:00:49 PM UTC 25 |
| Finished | Feb 09 02:00:52 PM UTC 25 |
| Peak memory | 214852 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162907085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_de bug_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.162907085 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_debug_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.2854554902 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4635346512 ps |
| CPU time | 9.58 seconds |
| Started | Feb 09 02:00:39 PM UTC 25 |
| Finished | Feb 09 02:00:49 PM UTC 25 |
| Peak memory | 216208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854554902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 0.rv_dm_sba_tl_access.2854554902 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1323979866 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 545554016 ps |
| CPU time | 2.41 seconds |
| Started | Feb 09 02:00:54 PM UTC 25 |
| Finished | Feb 09 02:00:58 PM UTC 25 |
| Peak memory | 254248 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323979866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1323979866 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.4008692380 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 556614079 ps |
| CPU time | 2.68 seconds |
| Started | Feb 09 02:01:05 PM UTC 25 |
| Finished | Feb 09 02:01:09 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008692380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstr actcmd_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.4008692380 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.4126600714 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 31672425 ps |
| CPU time | 0.93 seconds |
| Started | Feb 09 02:01:10 PM UTC 25 |
| Finished | Feb 09 02:01:12 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126600714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4126600714 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_autoincr_sba_tl_access.3906959854 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 37319841046 ps |
| CPU time | 46.19 seconds |
| Started | Feb 09 02:00:56 PM UTC 25 |
| Finished | Feb 09 02:01:44 PM UTC 25 |
| Peak memory | 232576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906959854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3906959854 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.884463467 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 9346608611 ps |
| CPU time | 32.84 seconds |
| Started | Feb 09 02:00:56 PM UTC 25 |
| Finished | Feb 09 02:01:31 PM UTC 25 |
| Peak memory | 226496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884463467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sb a_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.884463467 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.3573442659 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 148978227 ps |
| CPU time | 1.96 seconds |
| Started | Feb 09 02:00:59 PM UTC 25 |
| Finished | Feb 09 02:01:02 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573442659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmder r_exception_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3573442659 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_cmderr_exception/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.2886124599 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 489071347 ps |
| CPU time | 3.15 seconds |
| Started | Feb 09 02:01:01 PM UTC 25 |
| Finished | Feb 09 02:01:05 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886124599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmder r_halt_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2886124599 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.4178806251 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 544177719 ps |
| CPU time | 2.2 seconds |
| Started | Feb 09 02:00:57 PM UTC 25 |
| Finished | Feb 09 02:01:01 PM UTC 25 |
| Peak memory | 215700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178806251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmder r_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.4178806251 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.2588724400 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 198477116 ps |
| CPU time | 1.18 seconds |
| Started | Feb 09 02:01:02 PM UTC 25 |
| Finished | Feb 09 02:01:04 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588724400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataa ddr_rw_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2588724400 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3972618868 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 15172851641 ps |
| CPU time | 28.77 seconds |
| Started | Feb 09 02:00:55 PM UTC 25 |
| Finished | Feb 09 02:01:25 PM UTC 25 |
| Peak memory | 226380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972618868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl_access.3972618868 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.3177781912 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 481670441 ps |
| CPU time | 1.32 seconds |
| Started | Feb 09 02:01:02 PM UTC 25 |
| Finished | Feb 09 02:01:04 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177781912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_ resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3177781912 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.134076230 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1176151817 ps |
| CPU time | 1.54 seconds |
| Started | Feb 09 02:01:00 PM UTC 25 |
| Finished | Feb 09 02:01:02 PM UTC 25 |
| Peak memory | 215052 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134076230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_u navail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.rv_dm_hart_unavail.134076230 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1892465173 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 297642005 ps |
| CPU time | 2.13 seconds |
| Started | Feb 09 02:01:03 PM UTC 25 |
| Finished | Feb 09 02:01:06 PM UTC 25 |
| Peak memory | 215640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892465173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_ dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1892465173 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.96094994 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 177835008 ps |
| CPU time | 1.82 seconds |
| Started | Feb 09 02:01:05 PM UTC 25 |
| Finished | Feb 09 02:01:08 PM UTC 25 |
| Peak memory | 214992 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96094994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dt m_hard_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.96094994 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1367550236 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 249163223 ps |
| CPU time | 2.33 seconds |
| Started | Feb 09 02:01:03 PM UTC 25 |
| Finished | Feb 09 02:01:06 PM UTC 25 |
| Peak memory | 215768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367550236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_ dtm_idle_hint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1367550236 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.2591387131 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 296593480 ps |
| CPU time | 2.93 seconds |
| Started | Feb 09 02:00:59 PM UTC 25 |
| Finished | Feb 09 02:01:03 PM UTC 25 |
| Peak memory | 215724 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591387131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_t l_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.v db -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2591387131 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.4065082230 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3015791965 ps |
| CPU time | 7.64 seconds |
| Started | Feb 09 02:00:59 PM UTC 25 |
| Finished | Feb 09 02:01:07 PM UTC 25 |
| Peak memory | 216104 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065082230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_t l_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.4065082230 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1739814400 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 796937995 ps |
| CPU time | 2.18 seconds |
| Started | Feb 09 02:01:03 PM UTC 25 |
| Finished | Feb 09 02:01:06 PM UTC 25 |
| Peak memory | 226004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739814400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmre set_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 1.rv_dm_ndmreset_req.1739814400 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_ndmreset_req/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.2772910088 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 796608786 ps |
| CPU time | 5.66 seconds |
| Started | Feb 09 02:01:06 PM UTC 25 |
| Finished | Feb 09 02:01:13 PM UTC 25 |
| Peak memory | 215768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772910088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progb uf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2772910088 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.440509360 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 87448050 ps |
| CPU time | 1.37 seconds |
| Started | Feb 09 02:01:06 PM UTC 25 |
| Finished | Feb 09 02:01:09 PM UTC 25 |
| Peak memory | 224788 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440509360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_re ad_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm _log /dev/null -cm_name 1.rv_dm_rom_read_access.440509360 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_rom_read_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.3128957448 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3022904208 ps |
| CPU time | 4.38 seconds |
| Started | Feb 09 02:00:55 PM UTC 25 |
| Finished | Feb 09 02:01:01 PM UTC 25 |
| Peak memory | 216300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128957448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 1.rv_dm_sba_tl_access.3128957448 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_smoke.1780242665 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 5129730378 ps |
| CPU time | 17.92 seconds |
| Started | Feb 09 02:00:55 PM UTC 25 |
| Finished | Feb 09 02:01:14 PM UTC 25 |
| Peak memory | 216108 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780242665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 1.rv_dm_smoke.1780242665 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.2281939326 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 231035628928 ps |
| CPU time | 2155.73 seconds |
| Started | Feb 09 02:01:09 PM UTC 25 |
| Finished | Feb 09 02:37:28 PM UTC 25 |
| Peak memory | 264320 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2281939326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.2281939326 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.2459399038 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 137926794 ps |
| CPU time | 1.17 seconds |
| Started | Feb 09 02:02:05 PM UTC 25 |
| Finished | Feb 09 02:02:08 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459399038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2459399038 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_autoincr_sba_tl_access.1939227103 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3215099641 ps |
| CPU time | 21.41 seconds |
| Started | Feb 09 02:02:04 PM UTC 25 |
| Finished | Feb 09 02:02:27 PM UTC 25 |
| Peak memory | 226504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939227103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1939227103 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.3397756253 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 6404012796 ps |
| CPU time | 11.97 seconds |
| Started | Feb 09 02:02:01 PM UTC 25 |
| Finished | Feb 09 02:02:14 PM UTC 25 |
| Peak memory | 226452 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397756253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 10.rv_dm_sba_tl_access.3397756253 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.3181570597 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 56597987 ps |
| CPU time | 1.34 seconds |
| Started | Feb 09 02:02:11 PM UTC 25 |
| Finished | Feb 09 02:02:13 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181570597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3181570597 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/11.rv_dm_autoincr_sba_tl_access.2494302942 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3291769627 ps |
| CPU time | 12.28 seconds |
| Started | Feb 09 02:02:11 PM UTC 25 |
| Finished | Feb 09 02:02:24 PM UTC 25 |
| Peak memory | 226700 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494302942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2494302942 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.857930647 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4325064032 ps |
| CPU time | 27.32 seconds |
| Started | Feb 09 02:02:10 PM UTC 25 |
| Finished | Feb 09 02:02:38 PM UTC 25 |
| Peak memory | 226492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857930647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sb a_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.857930647 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3865923652 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 3734361705 ps |
| CPU time | 13.13 seconds |
| Started | Feb 09 02:02:09 PM UTC 25 |
| Finished | Feb 09 02:02:23 PM UTC 25 |
| Peak memory | 226436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865923652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl_access.3865923652 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.3159975521 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 11142963963 ps |
| CPU time | 36.07 seconds |
| Started | Feb 09 02:02:06 PM UTC 25 |
| Finished | Feb 09 02:02:44 PM UTC 25 |
| Peak memory | 226632 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159975521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 11.rv_dm_sba_tl_access.3159975521 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.2151306744 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 152435411 ps |
| CPU time | 1.44 seconds |
| Started | Feb 09 02:02:18 PM UTC 25 |
| Finished | Feb 09 02:02:20 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151306744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2151306744 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.3988671672 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 10977441049 ps |
| CPU time | 34.79 seconds |
| Started | Feb 09 02:02:15 PM UTC 25 |
| Finished | Feb 09 02:02:52 PM UTC 25 |
| Peak memory | 226624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988671672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3988671672 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.2140050873 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1042954020 ps |
| CPU time | 3.06 seconds |
| Started | Feb 09 02:02:14 PM UTC 25 |
| Finished | Feb 09 02:02:19 PM UTC 25 |
| Peak memory | 216076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140050873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2140050873 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.3511142238 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 7498956978 ps |
| CPU time | 35.7 seconds |
| Started | Feb 09 02:02:13 PM UTC 25 |
| Finished | Feb 09 02:02:50 PM UTC 25 |
| Peak memory | 226800 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511142238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 12.rv_dm_sba_tl_access.3511142238 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.2388095650 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 78926849 ps |
| CPU time | 1.17 seconds |
| Started | Feb 09 02:02:25 PM UTC 25 |
| Finished | Feb 09 02:02:27 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388095650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2388095650 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/13.rv_dm_autoincr_sba_tl_access.4265505748 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 28477020424 ps |
| CPU time | 20.26 seconds |
| Started | Feb 09 02:02:22 PM UTC 25 |
| Finished | Feb 09 02:02:43 PM UTC 25 |
| Peak memory | 226436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265505748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.4265505748 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3638017835 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2177505897 ps |
| CPU time | 5.72 seconds |
| Started | Feb 09 02:02:21 PM UTC 25 |
| Finished | Feb 09 02:02:27 PM UTC 25 |
| Peak memory | 216492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638017835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_tl_access.3638017835 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.362431639 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 15746668785 ps |
| CPU time | 18.05 seconds |
| Started | Feb 09 02:02:20 PM UTC 25 |
| Finished | Feb 09 02:02:39 PM UTC 25 |
| Peak memory | 228532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362431639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl _access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 13.rv_dm_sba_tl_access.362431639 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.518581740 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 8443034432 ps |
| CPU time | 23.81 seconds |
| Started | Feb 09 02:02:24 PM UTC 25 |
| Finished | Feb 09 02:02:49 PM UTC 25 |
| Peak memory | 216364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518581740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.518581740 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.4050868138 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 69773509 ps |
| CPU time | 1.31 seconds |
| Started | Feb 09 02:02:34 PM UTC 25 |
| Finished | Feb 09 02:02:37 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050868138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4050868138 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1917410308 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 3241442668 ps |
| CPU time | 7.66 seconds |
| Started | Feb 09 02:02:28 PM UTC 25 |
| Finished | Feb 09 02:02:37 PM UTC 25 |
| Peak memory | 226448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917410308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl_access.1917410308 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.504883300 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2686938921 ps |
| CPU time | 5.58 seconds |
| Started | Feb 09 02:02:33 PM UTC 25 |
| Finished | Feb 09 02:02:40 PM UTC 25 |
| Peak memory | 216096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504883300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.504883300 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.1746220962 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 70213594 ps |
| CPU time | 1.45 seconds |
| Started | Feb 09 02:02:41 PM UTC 25 |
| Finished | Feb 09 02:02:43 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746220962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1746220962 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3134957837 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 80666132609 ps |
| CPU time | 77.92 seconds |
| Started | Feb 09 02:02:39 PM UTC 25 |
| Finished | Feb 09 02:03:58 PM UTC 25 |
| Peak memory | 226424 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134957837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3134957837 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.512907379 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 5806643248 ps |
| CPU time | 12.31 seconds |
| Started | Feb 09 02:02:38 PM UTC 25 |
| Finished | Feb 09 02:02:51 PM UTC 25 |
| Peak memory | 228584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512907379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sb a_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.512907379 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3890540082 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 3962017438 ps |
| CPU time | 9.14 seconds |
| Started | Feb 09 02:02:38 PM UTC 25 |
| Finished | Feb 09 02:02:48 PM UTC 25 |
| Peak memory | 226564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890540082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl_access.3890540082 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.3009303290 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 117127152 ps |
| CPU time | 1.65 seconds |
| Started | Feb 09 02:02:46 PM UTC 25 |
| Finished | Feb 09 02:02:49 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009303290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3009303290 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3287636531 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3931111388 ps |
| CPU time | 20.64 seconds |
| Started | Feb 09 02:02:44 PM UTC 25 |
| Finished | Feb 09 02:03:06 PM UTC 25 |
| Peak memory | 226560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287636531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3287636531 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.4098389259 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 883713831 ps |
| CPU time | 6.18 seconds |
| Started | Feb 09 02:02:42 PM UTC 25 |
| Finished | Feb 09 02:02:49 PM UTC 25 |
| Peak memory | 216184 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098389259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl_access.4098389259 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.4093191167 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1463193967 ps |
| CPU time | 5.99 seconds |
| Started | Feb 09 02:02:42 PM UTC 25 |
| Finished | Feb 09 02:02:49 PM UTC 25 |
| Peak memory | 215980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093191167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 16.rv_dm_sba_tl_access.4093191167 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3212114230 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2090202374 ps |
| CPU time | 9.1 seconds |
| Started | Feb 09 02:02:45 PM UTC 25 |
| Finished | Feb 09 02:02:55 PM UTC 25 |
| Peak memory | 226448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212114230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3212114230 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.698930091 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 102072358 ps |
| CPU time | 1.18 seconds |
| Started | Feb 09 02:02:50 PM UTC 25 |
| Finished | Feb 09 02:02:52 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698930091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.698930091 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.130386171 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3301072084 ps |
| CPU time | 3.1 seconds |
| Started | Feb 09 02:02:48 PM UTC 25 |
| Finished | Feb 09 02:02:53 PM UTC 25 |
| Peak memory | 216204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130386171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sb a_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.130386171 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.571130169 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3454246928 ps |
| CPU time | 7.36 seconds |
| Started | Feb 09 02:02:47 PM UTC 25 |
| Finished | Feb 09 02:02:56 PM UTC 25 |
| Peak memory | 226432 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571130169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_S EQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl_access.571130169 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.453911902 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4340458458 ps |
| CPU time | 16.18 seconds |
| Started | Feb 09 02:02:46 PM UTC 25 |
| Finished | Feb 09 02:03:04 PM UTC 25 |
| Peak memory | 226440 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453911902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl _access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 17.rv_dm_sba_tl_access.453911902 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.3595072807 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6161002678 ps |
| CPU time | 9.65 seconds |
| Started | Feb 09 02:02:50 PM UTC 25 |
| Finished | Feb 09 02:03:00 PM UTC 25 |
| Peak memory | 216080 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595072807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3595072807 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.2862998871 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 42544449 ps |
| CPU time | 1.2 seconds |
| Started | Feb 09 02:02:53 PM UTC 25 |
| Finished | Feb 09 02:02:56 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862998871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2862998871 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3400994137 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 12263436196 ps |
| CPU time | 29.14 seconds |
| Started | Feb 09 02:02:51 PM UTC 25 |
| Finished | Feb 09 02:03:22 PM UTC 25 |
| Peak memory | 226512 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400994137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3400994137 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.4211538939 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 8566601734 ps |
| CPU time | 43.36 seconds |
| Started | Feb 09 02:02:50 PM UTC 25 |
| Finished | Feb 09 02:03:35 PM UTC 25 |
| Peak memory | 226624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211538939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.4211538939 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.5406044 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1322904184 ps |
| CPU time | 3.67 seconds |
| Started | Feb 09 02:02:50 PM UTC 25 |
| Finished | Feb 09 02:02:55 PM UTC 25 |
| Peak memory | 216060 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5406044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl_access.5406044 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1126667169 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1179105578 ps |
| CPU time | 4.78 seconds |
| Started | Feb 09 02:02:50 PM UTC 25 |
| Finished | Feb 09 02:02:56 PM UTC 25 |
| Peak memory | 216176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126667169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 18.rv_dm_sba_tl_access.1126667169 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.571139373 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2945000002 ps |
| CPU time | 18.62 seconds |
| Started | Feb 09 02:02:52 PM UTC 25 |
| Finished | Feb 09 02:03:12 PM UTC 25 |
| Peak memory | 226348 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571139373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.571139373 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.965557258 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 49393806 ps |
| CPU time | 1.15 seconds |
| Started | Feb 09 02:02:57 PM UTC 25 |
| Finished | Feb 09 02:02:59 PM UTC 25 |
| Peak memory | 214728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965557258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.965557258 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1067129288 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1471045879 ps |
| CPU time | 7.01 seconds |
| Started | Feb 09 02:02:55 PM UTC 25 |
| Finished | Feb 09 02:03:04 PM UTC 25 |
| Peak memory | 226364 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067129288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1067129288 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4278947930 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5503007236 ps |
| CPU time | 18.19 seconds |
| Started | Feb 09 02:02:53 PM UTC 25 |
| Finished | Feb 09 02:03:13 PM UTC 25 |
| Peak memory | 226448 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278947930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl_access.4278947930 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3584035925 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 65709534 ps |
| CPU time | 1.16 seconds |
| Started | Feb 09 02:01:15 PM UTC 25 |
| Finished | Feb 09 02:01:18 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584035925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3584035925 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2489645269 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2286906540 ps |
| CPU time | 6.53 seconds |
| Started | Feb 09 02:01:12 PM UTC 25 |
| Finished | Feb 09 02:01:19 PM UTC 25 |
| Peak memory | 226504 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489645269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2489645269 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.898049783 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 10417245685 ps |
| CPU time | 19.72 seconds |
| Started | Feb 09 02:01:11 PM UTC 25 |
| Finished | Feb 09 02:01:32 PM UTC 25 |
| Peak memory | 226688 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898049783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sb a_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb - cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.898049783 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4069895647 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 9004745799 ps |
| CPU time | 12.63 seconds |
| Started | Feb 09 02:01:11 PM UTC 25 |
| Finished | Feb 09 02:01:25 PM UTC 25 |
| Peak memory | 228776 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069895647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_access.4069895647 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2325642441 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 203058948 ps |
| CPU time | 1.57 seconds |
| Started | Feb 09 02:01:13 PM UTC 25 |
| Finished | Feb 09 02:01:16 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325642441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_ resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.2325642441 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3927840347 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1040942413 ps |
| CPU time | 3.17 seconds |
| Started | Feb 09 02:01:12 PM UTC 25 |
| Finished | Feb 09 02:01:16 PM UTC 25 |
| Peak memory | 215956 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927840347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_ unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 2.rv_dm_hart_unavail.3927840347 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.985741025 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4855214042 ps |
| CPU time | 7.73 seconds |
| Started | Feb 09 02:01:10 PM UTC 25 |
| Finished | Feb 09 02:01:19 PM UTC 25 |
| Peak memory | 216280 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985741025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl _access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 2.rv_dm_sba_tl_access.985741025 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3555990388 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2970890034 ps |
| CPU time | 4.93 seconds |
| Started | Feb 09 02:01:14 PM UTC 25 |
| Finished | Feb 09 02:01:21 PM UTC 25 |
| Peak memory | 254624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555990388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3555990388 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.1121120995 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 134620877 ps |
| CPU time | 1.65 seconds |
| Started | Feb 09 02:02:57 PM UTC 25 |
| Finished | Feb 09 02:02:59 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121120995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1121120995 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.4189127961 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 88536115 ps |
| CPU time | 1.15 seconds |
| Started | Feb 09 02:03:00 PM UTC 25 |
| Finished | Feb 09 02:03:02 PM UTC 25 |
| Peak memory | 214652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189127961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4189127961 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.1074247542 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2260908705 ps |
| CPU time | 15.75 seconds |
| Started | Feb 09 02:02:57 PM UTC 25 |
| Finished | Feb 09 02:03:14 PM UTC 25 |
| Peak memory | 226444 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074247542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1074247542 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2454151978 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 193936682 ps |
| CPU time | 1.24 seconds |
| Started | Feb 09 02:03:01 PM UTC 25 |
| Finished | Feb 09 02:03:03 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454151978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2454151978 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1023108057 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 108371437 ps |
| CPU time | 1.62 seconds |
| Started | Feb 09 02:03:03 PM UTC 25 |
| Finished | Feb 09 02:03:06 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023108057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1023108057 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.2093311503 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1810001580 ps |
| CPU time | 2.63 seconds |
| Started | Feb 09 02:03:02 PM UTC 25 |
| Finished | Feb 09 02:03:06 PM UTC 25 |
| Peak memory | 226332 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093311503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2093311503 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2651241061 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 51329397 ps |
| CPU time | 1.15 seconds |
| Started | Feb 09 02:03:04 PM UTC 25 |
| Finished | Feb 09 02:03:07 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651241061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2651241061 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.192712099 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 9087453274 ps |
| CPU time | 34 seconds |
| Started | Feb 09 02:03:03 PM UTC 25 |
| Finished | Feb 09 02:03:39 PM UTC 25 |
| Peak memory | 226416 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192712099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_te st +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.192712099 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1282940441 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 105522090 ps |
| CPU time | 1.26 seconds |
| Started | Feb 09 02:03:04 PM UTC 25 |
| Finished | Feb 09 02:03:07 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282940441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1282940441 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2745780611 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 5652074402 ps |
| CPU time | 12.58 seconds |
| Started | Feb 09 02:03:04 PM UTC 25 |
| Finished | Feb 09 02:03:18 PM UTC 25 |
| Peak memory | 216096 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745780611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2745780611 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.790544743 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 44846610 ps |
| CPU time | 1.06 seconds |
| Started | Feb 09 02:03:07 PM UTC 25 |
| Finished | Feb 09 02:03:09 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790544743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.790544743 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3775228770 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 66521458 ps |
| CPU time | 1.42 seconds |
| Started | Feb 09 02:03:07 PM UTC 25 |
| Finished | Feb 09 02:03:09 PM UTC 25 |
| Peak memory | 214928 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775228770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3775228770 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.3834633718 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4760472282 ps |
| CPU time | 18.18 seconds |
| Started | Feb 09 02:03:07 PM UTC 25 |
| Finished | Feb 09 02:03:26 PM UTC 25 |
| Peak memory | 216176 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834633718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3834633718 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.2196522447 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 118182168 ps |
| CPU time | 1.43 seconds |
| Started | Feb 09 02:03:08 PM UTC 25 |
| Finished | Feb 09 02:03:10 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196522447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2196522447 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.691675062 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 130874015 ps |
| CPU time | 1.08 seconds |
| Started | Feb 09 02:03:09 PM UTC 25 |
| Finished | Feb 09 02:03:11 PM UTC 25 |
| Peak memory | 214872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691675062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.691675062 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.4242080737 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3188608231 ps |
| CPU time | 4.72 seconds |
| Started | Feb 09 02:03:08 PM UTC 25 |
| Finished | Feb 09 02:03:14 PM UTC 25 |
| Peak memory | 226340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242080737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.4242080737 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.146112985 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 55519829 ps |
| CPU time | 1.19 seconds |
| Started | Feb 09 02:01:23 PM UTC 25 |
| Finished | Feb 09 02:01:26 PM UTC 25 |
| Peak memory | 214872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146112985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.146112985 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.3104353621 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2463392324 ps |
| CPU time | 5.71 seconds |
| Started | Feb 09 02:01:19 PM UTC 25 |
| Finished | Feb 09 02:01:26 PM UTC 25 |
| Peak memory | 228752 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104353621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3104353621 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3248232767 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 10202400679 ps |
| CPU time | 26.28 seconds |
| Started | Feb 09 02:01:17 PM UTC 25 |
| Finished | Feb 09 02:01:45 PM UTC 25 |
| Peak memory | 216300 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248232767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3248232767 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3386698883 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2668470589 ps |
| CPU time | 4 seconds |
| Started | Feb 09 02:01:17 PM UTC 25 |
| Finished | Feb 09 02:01:22 PM UTC 25 |
| Peak memory | 226472 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386698883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl_access.3386698883 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1515742197 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 435013280 ps |
| CPU time | 1.32 seconds |
| Started | Feb 09 02:01:19 PM UTC 25 |
| Finished | Feb 09 02:01:21 PM UTC 25 |
| Peak memory | 214988 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515742197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_ unavail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 3.rv_dm_hart_unavail.1515742197 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_hart_unavail/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.2412109261 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 5628646103 ps |
| CPU time | 19.68 seconds |
| Started | Feb 09 02:01:17 PM UTC 25 |
| Finished | Feb 09 02:01:38 PM UTC 25 |
| Peak memory | 226496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412109261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 3.rv_dm_sba_tl_access.2412109261 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.1927726204 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 996878600 ps |
| CPU time | 2.02 seconds |
| Started | Feb 09 02:01:22 PM UTC 25 |
| Finished | Feb 09 02:01:26 PM UTC 25 |
| Peak memory | 254464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927726204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1927726204 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3404397557 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 340242949965 ps |
| CPU time | 1270.81 seconds |
| Started | Feb 09 02:01:21 PM UTC 25 |
| Finished | Feb 09 02:22:46 PM UTC 25 |
| Peak memory | 250008 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3404397557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.3404397557 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.3673661111 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 93924769 ps |
| CPU time | 1.28 seconds |
| Started | Feb 09 02:03:10 PM UTC 25 |
| Finished | Feb 09 02:03:13 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673661111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3673661111 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.2327290451 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 66393368 ps |
| CPU time | 1.28 seconds |
| Started | Feb 09 02:03:12 PM UTC 25 |
| Finished | Feb 09 02:03:15 PM UTC 25 |
| Peak memory | 214660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327290451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2327290451 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.1547284123 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2279634406 ps |
| CPU time | 16.37 seconds |
| Started | Feb 09 02:03:11 PM UTC 25 |
| Finished | Feb 09 02:03:29 PM UTC 25 |
| Peak memory | 226340 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547284123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1547284123 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3863285495 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 83075776 ps |
| CPU time | 1.24 seconds |
| Started | Feb 09 02:03:14 PM UTC 25 |
| Finished | Feb 09 02:03:16 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863285495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3863285495 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.3758237845 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 135763281 ps |
| CPU time | 1.16 seconds |
| Started | Feb 09 02:03:14 PM UTC 25 |
| Finished | Feb 09 02:03:16 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758237845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3758237845 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3402952421 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 86619916 ps |
| CPU time | 1.28 seconds |
| Started | Feb 09 02:03:15 PM UTC 25 |
| Finished | Feb 09 02:03:17 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402952421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3402952421 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2921824624 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4570489814 ps |
| CPU time | 6.73 seconds |
| Started | Feb 09 02:03:15 PM UTC 25 |
| Finished | Feb 09 02:03:23 PM UTC 25 |
| Peak memory | 226608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921824624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2921824624 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3744074044 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 103848335 ps |
| CPU time | 1.15 seconds |
| Started | Feb 09 02:03:17 PM UTC 25 |
| Finished | Feb 09 02:03:19 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744074044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3744074044 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.3296431939 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 41493864 ps |
| CPU time | 1.25 seconds |
| Started | Feb 09 02:03:18 PM UTC 25 |
| Finished | Feb 09 02:03:21 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296431939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3296431939 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3203895157 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5464261144 ps |
| CPU time | 10.11 seconds |
| Started | Feb 09 02:03:17 PM UTC 25 |
| Finished | Feb 09 02:03:29 PM UTC 25 |
| Peak memory | 226396 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203895157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3203895157 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3918076512 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 91572258 ps |
| CPU time | 1.19 seconds |
| Started | Feb 09 02:03:20 PM UTC 25 |
| Finished | Feb 09 02:03:23 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918076512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3918076512 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3776358735 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 132538882 ps |
| CPU time | 1.79 seconds |
| Started | Feb 09 02:03:22 PM UTC 25 |
| Finished | Feb 09 02:03:25 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776358735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3776358735 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2725133099 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 57701179 ps |
| CPU time | 1.12 seconds |
| Started | Feb 09 02:03:23 PM UTC 25 |
| Finished | Feb 09 02:03:25 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725133099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2725133099 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.2341608540 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2902473163 ps |
| CPU time | 4.9 seconds |
| Started | Feb 09 02:03:22 PM UTC 25 |
| Finished | Feb 09 02:03:28 PM UTC 25 |
| Peak memory | 226400 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341608540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2341608540 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.3466583926 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 39628458 ps |
| CPU time | 1.23 seconds |
| Started | Feb 09 02:01:32 PM UTC 25 |
| Finished | Feb 09 02:01:34 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466583926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3466583926 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.1416700342 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 7103633016 ps |
| CPU time | 18.22 seconds |
| Started | Feb 09 02:01:26 PM UTC 25 |
| Finished | Feb 09 02:01:46 PM UTC 25 |
| Peak memory | 226428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416700342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1416700342 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.2973204285 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 7006317503 ps |
| CPU time | 14.68 seconds |
| Started | Feb 09 02:01:26 PM UTC 25 |
| Finished | Feb 09 02:01:42 PM UTC 25 |
| Peak memory | 216180 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973204285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2973204285 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2749457950 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2675394381 ps |
| CPU time | 10.01 seconds |
| Started | Feb 09 02:01:25 PM UTC 25 |
| Finished | Feb 09 02:01:37 PM UTC 25 |
| Peak memory | 216204 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749457950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_access.2749457950 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2713745582 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 719555359 ps |
| CPU time | 5.14 seconds |
| Started | Feb 09 02:01:26 PM UTC 25 |
| Finished | Feb 09 02:01:33 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713745582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_ resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.2713745582 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.4166073164 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5678762821 ps |
| CPU time | 21.93 seconds |
| Started | Feb 09 02:01:24 PM UTC 25 |
| Finished | Feb 09 02:01:48 PM UTC 25 |
| Peak memory | 216208 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166073164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 4.rv_dm_sba_tl_access.4166073164 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.3767647619 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 997179815 ps |
| CPU time | 3.99 seconds |
| Started | Feb 09 02:01:30 PM UTC 25 |
| Finished | Feb 09 02:01:35 PM UTC 25 |
| Peak memory | 254392 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767647619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3767647619 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1631190580 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2725681110 ps |
| CPU time | 17.96 seconds |
| Started | Feb 09 02:01:26 PM UTC 25 |
| Finished | Feb 09 02:01:46 PM UTC 25 |
| Peak memory | 226344 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631190580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1631190580 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.1740421300 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 41171131505 ps |
| CPU time | 430.51 seconds |
| Started | Feb 09 02:01:28 PM UTC 25 |
| Finished | Feb 09 02:08:44 PM UTC 25 |
| Peak memory | 244004 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1740421300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.1740421300 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2092760102 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 236993149 ps |
| CPU time | 1.17 seconds |
| Started | Feb 09 02:03:24 PM UTC 25 |
| Finished | Feb 09 02:03:26 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092760102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2092760102 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2897362792 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 6661985678 ps |
| CPU time | 10.74 seconds |
| Started | Feb 09 02:03:24 PM UTC 25 |
| Finished | Feb 09 02:03:36 PM UTC 25 |
| Peak memory | 216032 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897362792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2897362792 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.1649283199 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 69665291 ps |
| CPU time | 1.12 seconds |
| Started | Feb 09 02:03:25 PM UTC 25 |
| Finished | Feb 09 02:03:27 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649283199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1649283199 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1305902803 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 58354169 ps |
| CPU time | 1.35 seconds |
| Started | Feb 09 02:03:26 PM UTC 25 |
| Finished | Feb 09 02:03:29 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305902803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1305902803 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.221334550 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 36247522 ps |
| CPU time | 1.1 seconds |
| Started | Feb 09 02:03:27 PM UTC 25 |
| Finished | Feb 09 02:03:30 PM UTC 25 |
| Peak memory | 214872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221334550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.221334550 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3978021474 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5421890463 ps |
| CPU time | 11.21 seconds |
| Started | Feb 09 02:03:27 PM UTC 25 |
| Finished | Feb 09 02:03:40 PM UTC 25 |
| Peak memory | 216076 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978021474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3978021474 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2415618552 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 98332647 ps |
| CPU time | 1.38 seconds |
| Started | Feb 09 02:03:29 PM UTC 25 |
| Finished | Feb 09 02:03:31 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415618552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2415618552 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.567793309 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 192052503 ps |
| CPU time | 1.08 seconds |
| Started | Feb 09 02:03:29 PM UTC 25 |
| Finished | Feb 09 02:03:31 PM UTC 25 |
| Peak memory | 214872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567793309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.567793309 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/45.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.807935801 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 133080889 ps |
| CPU time | 1.66 seconds |
| Started | Feb 09 02:03:30 PM UTC 25 |
| Finished | Feb 09 02:03:33 PM UTC 25 |
| Peak memory | 214872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807935801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.807935801 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/46.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3982101335 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 68856561 ps |
| CPU time | 1.14 seconds |
| Started | Feb 09 02:03:31 PM UTC 25 |
| Finished | Feb 09 02:03:33 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982101335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3982101335 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1756911659 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3304136852 ps |
| CPU time | 4.53 seconds |
| Started | Feb 09 02:03:30 PM UTC 25 |
| Finished | Feb 09 02:03:36 PM UTC 25 |
| Peak memory | 226380 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756911659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1756911659 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2805617243 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 56602930 ps |
| CPU time | 1.34 seconds |
| Started | Feb 09 02:03:32 PM UTC 25 |
| Finished | Feb 09 02:03:35 PM UTC 25 |
| Peak memory | 214868 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805617243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2805617243 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.3012197703 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3128788601 ps |
| CPU time | 4.82 seconds |
| Started | Feb 09 02:03:32 PM UTC 25 |
| Finished | Feb 09 02:03:38 PM UTC 25 |
| Peak memory | 226336 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012197703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3012197703 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.835287055 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 74397908 ps |
| CPU time | 1.08 seconds |
| Started | Feb 09 02:03:33 PM UTC 25 |
| Finished | Feb 09 02:03:36 PM UTC 25 |
| Peak memory | 214872 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835287055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.835287055 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/49.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1816080754 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 37154753 ps |
| CPU time | 1.15 seconds |
| Started | Feb 09 02:01:40 PM UTC 25 |
| Finished | Feb 09 02:01:43 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816080754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1816080754 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.2453960838 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2202689999 ps |
| CPU time | 4.78 seconds |
| Started | Feb 09 02:01:35 PM UTC 25 |
| Finished | Feb 09 02:01:41 PM UTC 25 |
| Peak memory | 226436 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453960838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2453960838 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1893371523 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1319623008 ps |
| CPU time | 6.52 seconds |
| Started | Feb 09 02:01:34 PM UTC 25 |
| Finished | Feb 09 02:01:42 PM UTC 25 |
| Peak memory | 216168 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893371523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_access.1893371523 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.4208453036 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 291068638 ps |
| CPU time | 2.16 seconds |
| Started | Feb 09 02:01:36 PM UTC 25 |
| Finished | Feb 09 02:01:39 PM UTC 25 |
| Peak memory | 215960 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208453036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_ resume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vd b -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.4208453036 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.160988983 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6708344466 ps |
| CPU time | 21.8 seconds |
| Started | Feb 09 02:01:33 PM UTC 25 |
| Finished | Feb 09 02:01:56 PM UTC 25 |
| Peak memory | 216312 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160988983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl _access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_l og /dev/null -cm_name 5.rv_dm_sba_tl_access.160988983 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3541026645 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4861025160 ps |
| CPU time | 19.31 seconds |
| Started | Feb 09 02:01:37 PM UTC 25 |
| Finished | Feb 09 02:01:58 PM UTC 25 |
| Peak memory | 226412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541026645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3541026645 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3339992464 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 249334044285 ps |
| CPU time | 404.15 seconds |
| Started | Feb 09 02:01:39 PM UTC 25 |
| Finished | Feb 09 02:08:29 PM UTC 25 |
| Peak memory | 237980 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3339992464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.3339992464 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1006000448 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 56469638 ps |
| CPU time | 1 seconds |
| Started | Feb 09 02:01:45 PM UTC 25 |
| Finished | Feb 09 02:01:48 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006000448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1006000448 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.1219645981 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 13043645094 ps |
| CPU time | 27.98 seconds |
| Started | Feb 09 02:01:44 PM UTC 25 |
| Finished | Feb 09 02:02:14 PM UTC 25 |
| Peak memory | 226660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219645981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1219645981 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.4155621921 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3320928811 ps |
| CPU time | 11.18 seconds |
| Started | Feb 09 02:01:44 PM UTC 25 |
| Finished | Feb 09 02:01:56 PM UTC 25 |
| Peak memory | 226560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155621921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4155621921 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3187033861 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2192412961 ps |
| CPU time | 6.63 seconds |
| Started | Feb 09 02:01:42 PM UTC 25 |
| Finished | Feb 09 02:01:50 PM UTC 25 |
| Peak memory | 216464 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187033861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_access.3187033861 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.689324940 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 166578768 ps |
| CPU time | 1.55 seconds |
| Started | Feb 09 02:01:44 PM UTC 25 |
| Finished | Feb 09 02:01:47 PM UTC 25 |
| Peak memory | 214884 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689324940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_r esume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.689324940 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2689451542 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1614061834 ps |
| CPU time | 7.17 seconds |
| Started | Feb 09 02:01:41 PM UTC 25 |
| Finished | Feb 09 02:01:50 PM UTC 25 |
| Peak memory | 226308 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689451542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 6.rv_dm_sba_tl_access.2689451542 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.2594217311 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 53708517989 ps |
| CPU time | 1204.52 seconds |
| Started | Feb 09 02:01:45 PM UTC 25 |
| Finished | Feb 09 02:22:03 PM UTC 25 |
| Peak memory | 248164 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2594217311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.2594217311 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3462353393 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 117599411 ps |
| CPU time | 1.23 seconds |
| Started | Feb 09 02:01:52 PM UTC 25 |
| Finished | Feb 09 02:01:54 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462353393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3462353393 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1041571585 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 12285298944 ps |
| CPU time | 22.39 seconds |
| Started | Feb 09 02:01:48 PM UTC 25 |
| Finished | Feb 09 02:02:12 PM UTC 25 |
| Peak memory | 230528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041571585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoi ncr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1041571585 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.967171480 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3613244093 ps |
| CPU time | 9.15 seconds |
| Started | Feb 09 02:01:47 PM UTC 25 |
| Finished | Feb 09 02:01:58 PM UTC 25 |
| Peak memory | 226476 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967171480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_S EQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl_access.967171480 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.187775514 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1256390394 ps |
| CPU time | 3.59 seconds |
| Started | Feb 09 02:01:48 PM UTC 25 |
| Finished | Feb 09 02:01:53 PM UTC 25 |
| Peak memory | 215768 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187775514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_r esume_whereto_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.187775514 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_halt_resume_whereto/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.747640257 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 23515134543 ps |
| CPU time | 298.08 seconds |
| Started | Feb 09 02:01:52 PM UTC 25 |
| Finished | Feb 09 02:06:54 PM UTC 25 |
| Peak memory | 233624 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=747640257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.747640257 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.3226120952 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 67262399 ps |
| CPU time | 1.26 seconds |
| Started | Feb 09 02:01:57 PM UTC 25 |
| Finished | Feb 09 02:02:00 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226120952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3226120952 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.2939928348 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5276837164 ps |
| CPU time | 4.92 seconds |
| Started | Feb 09 02:01:54 PM UTC 25 |
| Finished | Feb 09 02:02:00 PM UTC 25 |
| Peak memory | 226428 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939928348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2939928348 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3696723686 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1648136180 ps |
| CPU time | 10.84 seconds |
| Started | Feb 09 02:01:54 PM UTC 25 |
| Finished | Feb 09 02:02:06 PM UTC 25 |
| Peak memory | 226576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696723686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_ SEQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_access.3696723686 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.646708099 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 146712028924 ps |
| CPU time | 1578.02 seconds |
| Started | Feb 09 02:01:57 PM UTC 25 |
| Finished | Feb 09 02:28:31 PM UTC 25 |
| Peak memory | 256048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stres s_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=646708099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.646708099 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1862560065 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 40177727 ps |
| CPU time | 1.24 seconds |
| Started | Feb 09 02:02:01 PM UTC 25 |
| Finished | Feb 09 02:02:03 PM UTC 25 |
| Peak memory | 214808 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862560065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1862560065 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.2437149489 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1294340613 ps |
| CPU time | 9.02 seconds |
| Started | Feb 09 02:01:58 PM UTC 25 |
| Finished | Feb 09 02:02:09 PM UTC 25 |
| Peak memory | 226292 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437149489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_s ba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2437149489 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.415481565 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4240960077 ps |
| CPU time | 10.43 seconds |
| Started | Feb 09 02:01:58 PM UTC 25 |
| Finished | Feb 09 02:02:10 PM UTC 25 |
| Peak memory | 226728 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415481565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_S EQ=rv_dm_delayed_resp_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_access.415481565 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2932964200 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1075860967 ps |
| CPU time | 2.65 seconds |
| Started | Feb 09 02:01:57 PM UTC 25 |
| Finished | Feb 09 02:02:01 PM UTC 25 |
| Peak memory | 216068 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932964200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_t l_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default.vdb -cm_ log /dev/null -cm_name 9.rv_dm_sba_tl_access.2932964200 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_sba_tl_access/latest |
| Test location | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3178150048 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6058831382 ps |
| CPU time | 20.66 seconds |
| Started | Feb 09 02:01:59 PM UTC 25 |
| Finished | Feb 09 02:02:21 PM UTC 25 |
| Peak memory | 216172 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178150048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_t est +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3178150048 |
| Directory | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest |
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