| | | | | | | | | | | |
dv_base_reg_pkg::mubi32_cov::mubi_cg |
63 |
345 |
18.26 |
18.26 |
1 |
100 |
1 |
1 |
64 |
64 |
|
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg |
13 |
15 |
86.67 |
96.15 |
1 |
100 |
1 |
1 |
64 |
64 |
|
alert_esc_agent_pkg::alert_handshake_complete_cg |
3 |
3 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg |
14 |
14 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg |
24 |
24 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg |
2 |
2 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg |
4 |
4 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
tb.dut.u_reg_regs.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg |
2 |
2 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} |
1 |
1 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
tl_agent_pkg::pending_req_on_rst_cg |
2 |
2 |
100.00 |
83.33 |
1 |
100 |
1 |
1 |
64 |
64 |
|
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} |
137 |
137 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|
tl_agent_pkg::tl_d_chan_cov_cg |
5 |
5 |
100.00 |
100.00 |
1 |
100 |
1 |
1 |
64 |
64 |
|