| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 82.47 | 96.32 | 87.13 | 92.10 | 72.50 | 90.44 | 98.21 | 40.57 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 55.68 | 55.68 | 82.62 | 82.62 | 49.08 | 49.08 | 54.08 | 54.08 | 48.75 | 48.75 | 61.60 | 61.60 | 92.11 | 92.11 | 1.55 | 1.55 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.476113179 |
| 62.26 | 6.57 | 86.75 | 4.13 | 59.97 | 10.89 | 68.07 | 13.99 | 55.00 | 6.25 | 69.45 | 7.85 | 93.38 | 1.26 | 3.17 | 1.62 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2589069845 |
| 68.32 | 6.06 | 88.56 | 1.81 | 68.18 | 8.20 | 70.42 | 2.35 | 55.00 | 0.00 | 74.40 | 4.95 | 94.43 | 1.05 | 27.25 | 24.08 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2301892413 |
| 73.53 | 5.22 | 91.99 | 3.43 | 73.97 | 5.80 | 79.03 | 8.61 | 65.00 | 10.00 | 80.72 | 6.31 | 95.90 | 1.47 | 28.13 | 0.88 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.864359495 |
| 75.83 | 2.30 | 93.70 | 1.71 | 77.23 | 3.25 | 80.21 | 1.18 | 71.25 | 6.25 | 84.13 | 3.41 | 95.90 | 0.00 | 28.42 | 0.29 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all.2491407117 |
| 77.13 | 1.30 | 93.75 | 0.05 | 79.35 | 2.12 | 86.47 | 6.26 | 71.25 | 0.00 | 84.30 | 0.17 | 96.00 | 0.11 | 28.79 | 0.37 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.774849801 |
| 77.79 | 0.66 | 93.80 | 0.05 | 80.76 | 1.41 | 87.31 | 0.84 | 71.25 | 0.00 | 84.64 | 0.34 | 96.21 | 0.21 | 30.56 | 1.77 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2324784068 |
| 78.35 | 0.56 | 94.31 | 0.50 | 81.90 | 1.13 | 87.35 | 0.04 | 72.50 | 1.25 | 85.49 | 0.85 | 96.21 | 0.00 | 30.71 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2277188597 |
| 78.83 | 0.48 | 94.31 | 0.00 | 81.90 | 0.00 | 90.71 | 3.36 | 72.50 | 0.00 | 85.49 | 0.00 | 96.21 | 0.00 | 30.71 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.1599876082 |
| 79.30 | 0.47 | 94.51 | 0.20 | 83.31 | 1.41 | 91.18 | 0.46 | 72.50 | 0.00 | 86.35 | 0.85 | 96.32 | 0.11 | 30.93 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.2043718837 |
| 79.63 | 0.33 | 94.86 | 0.35 | 83.88 | 0.57 | 91.26 | 0.08 | 72.50 | 0.00 | 87.20 | 0.85 | 96.32 | 0.00 | 31.37 | 0.44 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.177449669 |
| 79.92 | 0.30 | 95.31 | 0.45 | 84.72 | 0.85 | 91.51 | 0.25 | 72.50 | 0.00 | 87.71 | 0.51 | 96.32 | 0.00 | 31.37 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1821280097 |
| 80.15 | 0.23 | 95.72 | 0.40 | 85.15 | 0.42 | 91.51 | 0.00 | 72.50 | 0.00 | 88.40 | 0.68 | 96.32 | 0.00 | 31.44 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.732687478 |
| 80.34 | 0.20 | 95.87 | 0.15 | 85.57 | 0.42 | 91.72 | 0.21 | 72.50 | 0.00 | 88.91 | 0.51 | 96.32 | 0.00 | 31.52 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.770579637 |
| 80.51 | 0.16 | 95.92 | 0.05 | 85.71 | 0.14 | 91.89 | 0.17 | 72.50 | 0.00 | 89.25 | 0.34 | 96.32 | 0.00 | 31.96 | 0.44 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1533430602 |
| 80.67 | 0.16 | 95.92 | 0.00 | 85.71 | 0.00 | 91.97 | 0.08 | 72.50 | 0.00 | 89.25 | 0.00 | 97.37 | 1.05 | 31.96 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1214622237 |
| 80.82 | 0.15 | 96.07 | 0.15 | 86.28 | 0.57 | 91.97 | 0.00 | 72.50 | 0.00 | 89.59 | 0.34 | 97.37 | 0.00 | 31.96 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2176585677 |
| 80.92 | 0.09 | 96.07 | 0.00 | 86.28 | 0.00 | 91.97 | 0.00 | 72.50 | 0.00 | 89.59 | 0.00 | 97.37 | 0.00 | 32.62 | 0.66 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4278428303 |
| 81.00 | 0.08 | 96.07 | 0.00 | 86.28 | 0.00 | 91.97 | 0.00 | 72.50 | 0.00 | 89.59 | 0.00 | 97.37 | 0.00 | 33.21 | 0.59 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.1876766762 |
| 81.08 | 0.08 | 96.07 | 0.00 | 86.56 | 0.28 | 91.97 | 0.00 | 72.50 | 0.00 | 89.59 | 0.00 | 97.37 | 0.00 | 33.51 | 0.29 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.970172436 |
| 81.16 | 0.08 | 96.12 | 0.05 | 86.70 | 0.14 | 92.02 | 0.04 | 72.50 | 0.00 | 89.93 | 0.34 | 97.37 | 0.00 | 33.51 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.364935057 |
| 81.24 | 0.07 | 96.12 | 0.00 | 86.85 | 0.14 | 92.10 | 0.08 | 72.50 | 0.00 | 89.93 | 0.00 | 97.37 | 0.00 | 33.80 | 0.29 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.2033360981 |
| 81.31 | 0.07 | 96.17 | 0.05 | 86.99 | 0.14 | 92.10 | 0.00 | 72.50 | 0.00 | 90.10 | 0.17 | 97.37 | 0.00 | 33.95 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1518409067 |
| 81.37 | 0.06 | 96.17 | 0.00 | 86.99 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.10 | 0.00 | 97.37 | 0.00 | 34.39 | 0.44 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.572770509 |
| 81.43 | 0.06 | 96.17 | 0.00 | 86.99 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.10 | 0.00 | 97.79 | 0.42 | 34.39 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.4189612210 |
| 81.48 | 0.04 | 96.17 | 0.00 | 87.13 | 0.14 | 92.10 | 0.00 | 72.50 | 0.00 | 90.10 | 0.00 | 97.79 | 0.00 | 34.54 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1062939061 |
| 81.51 | 0.03 | 96.22 | 0.05 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.27 | 0.17 | 97.79 | 0.00 | 34.54 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2223713213 |
| 81.54 | 0.03 | 96.27 | 0.05 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.17 | 97.79 | 0.00 | 34.54 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.2032060874 |
| 81.57 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 97.79 | 0.00 | 34.76 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.1637677186 |
| 81.60 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 97.79 | 0.00 | 34.98 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.4067317787 |
| 81.63 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 97.79 | 0.00 | 35.20 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3765127645 |
| 81.67 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 97.79 | 0.00 | 35.42 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.1558204855 |
| 81.70 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 97.79 | 0.00 | 35.64 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1194806234 |
| 81.73 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 97.79 | 0.00 | 35.86 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.297135172 |
| 81.76 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 97.79 | 0.00 | 36.08 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.2840637636 |
| 81.79 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 97.79 | 0.00 | 36.30 | 0.22 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.2627370640 |
| 81.82 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.00 | 0.21 | 36.30 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2889579930 |
| 81.85 | 0.03 | 96.27 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.21 | 36.30 | 0.00 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3010842781 |
| 81.88 | 0.03 | 96.32 | 0.05 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 36.45 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2386371965 |
| 81.90 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 36.60 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2872140517 |
| 81.92 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 36.75 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2753182130 |
| 81.94 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 36.89 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3441300837 |
| 81.96 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 37.04 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3533732167 |
| 81.99 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 37.19 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.2939836115 |
| 82.01 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 37.33 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.1766860363 |
| 82.03 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 37.48 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1285493755 |
| 82.05 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 37.63 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2802255606 |
| 82.07 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 37.78 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.3498658708 |
| 82.09 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 37.92 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.2017632538 |
| 82.11 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.07 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.3278932864 |
| 82.13 | 0.02 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.22 | 0.15 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.2006234611 |
| 82.14 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.29 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2654570836 |
| 82.15 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.37 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.1221418505 |
| 82.16 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.44 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.2906493645 |
| 82.17 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.51 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2434680628 |
| 82.18 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.59 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1268122504 |
| 82.20 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.66 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.397909550 |
| 82.21 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.73 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.2684375967 |
| 82.22 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.81 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.628646149 |
| 82.23 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.88 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.1902734531 |
| 82.24 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 38.95 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.2941156328 |
| 82.25 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.03 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2025777317 |
| 82.26 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.10 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.1496341438 |
| 82.27 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.18 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1371730953 |
| 82.28 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.25 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.3284216745 |
| 82.29 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.32 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.2200083061 |
| 82.30 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.40 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1843681136 |
| 82.31 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.47 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1277640419 |
| 82.32 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.54 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1975360242 |
| 82.33 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.62 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.506008538 |
| 82.34 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.69 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.3949105975 |
| 82.35 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.76 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.2228969622 |
| 82.36 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.84 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.1191472296 |
| 82.37 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.91 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.130796245 |
| 82.38 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 39.99 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.235415833 |
| 82.40 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 40.06 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/35.rv_dm_stress_all.3271752616 |
| 82.41 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 40.13 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.3156914794 |
| 82.42 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 40.21 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1154293556 |
| 82.43 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 40.28 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/49.rv_dm_stress_all.111302142 |
| 82.44 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 40.35 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all.2324493402 |
| 82.45 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 40.43 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_sba_tl_access.25890947 |
| 82.46 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 40.50 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.1658756777 |
| 82.47 | 0.01 | 96.32 | 0.00 | 87.13 | 0.00 | 92.10 | 0.00 | 72.50 | 0.00 | 90.44 | 0.00 | 98.21 | 0.00 | 40.57 | 0.07 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.3786649800 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.177351292 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.734259663 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2581252778 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.1096792517 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.312708498 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2065486853 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2044884413 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3909193973 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3146942992 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.751789355 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4126956709 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.761587134 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.78249012 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.988410483 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.221052051 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1818366308 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3636032248 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2046686237 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.1303723630 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1703838649 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1538115361 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.67234256 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3174115451 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4060660707 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1971378944 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.868408706 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3785284050 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2100205138 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.2232871914 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.263673919 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.2923369032 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3713249453 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.452953217 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2853649553 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1160607965 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.325199697 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_tl_errors.1817445440 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3761032588 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_csr_rw.1272736642 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.206781850 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3675654577 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.134244221 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3731162393 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_errors.809422336 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4154980819 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3706667111 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_csr_rw.699691992 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2304098735 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1191708420 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1351033767 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3544519043 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_errors.74921210 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2403849786 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_csr_rw.3049363635 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2851303124 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1876183869 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3787226516 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3428110015 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_errors.3462074685 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3169093413 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3756194274 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.2704690721 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.779650464 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2729450882 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3770351172 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.37647770 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_errors.4143533955 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2102548558 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1062268430 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_csr_rw.3073396040 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3625232021 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3637201885 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2247478884 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2618084271 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_errors.1542380860 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1567242678 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.582292923 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_csr_rw.3869991767 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1519726663 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1350739127 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3942582894 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1824807567 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/16.rv_dm_tl_errors.121919193 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4205627900 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_csr_rw.2527171675 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2840934302 |
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| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.977810650 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1521113392 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2018820326 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.934157105 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_errors.2804579930 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2738294247 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1062760864 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_csr_rw.2806618563 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.759109996 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.425165165 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4106025181 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3579300476 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_errors.3021717802 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/19.rv_dm_tl_intg_err.832486433 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2593500587 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3507564888 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3505085710 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.972867023 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_rw.2013818146 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2372129199 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.640018527 |
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| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3890540082 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.3009303290 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3287636531 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.4098389259 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.4093191167 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3212114230 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.698930091 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_bad_sba_tl_access.130386171 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.571130169 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.453911902 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.3595072807 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.2862998871 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_autoincr_sba_tl_access.3400994137 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.4211538939 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.5406044 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.1126667169 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.571139373 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.965557258 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.1067129288 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4278947930 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3584035925 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2489645269 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.898049783 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4069895647 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.2325642441 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.3927840347 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.985741025 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.3555990388 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.1121120995 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.4189127961 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.1074247542 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2454151978 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.1023108057 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.2093311503 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2651241061 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.192712099 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.1282940441 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.2745780611 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.790544743 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3775228770 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.3834633718 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.2196522447 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.691675062 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/29.rv_dm_stress_all.4242080737 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.146112985 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.3104353621 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3248232767 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3386698883 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.1515742197 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.2412109261 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.1927726204 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3404397557 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.3673661111 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.2327290451 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/31.rv_dm_stress_all.1547284123 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3863285495 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.3758237845 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.3402952421 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.2921824624 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.3744074044 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.3296431939 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3203895157 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.3918076512 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.3776358735 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.2725133099 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.2341608540 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.3466583926 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.1416700342 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.2973204285 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2749457950 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2713745582 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.4166073164 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.3767647619 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.1631190580 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.1740421300 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.2092760102 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.2897362792 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.1649283199 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.1305902803 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.221334550 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3978021474 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.2415618552 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.567793309 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.807935801 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3982101335 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.1756911659 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.2805617243 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.3012197703 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/49.rv_dm_alert_test.835287055 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.1816080754 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.2453960838 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1893371523 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.4208453036 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.160988983 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.3541026645 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3339992464 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_alert_test.1006000448 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_autoincr_sba_tl_access.1219645981 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_bad_sba_tl_access.4155621921 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3187033861 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_halt_resume_whereto.689324940 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.2689451542 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.2594217311 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.3462353393 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.1041571585 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.967171480 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.187775514 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.747640257 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.3226120952 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.2939928348 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3696723686 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.646708099 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.1862560065 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.2437149489 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.415481565 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.2932964200 |
| /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.3178150048 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3533732167 | Feb 09 02:00:37 PM UTC 25 | Feb 09 02:00:41 PM UTC 25 | 948659379 ps | ||
| T2 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.1221418505 | Feb 09 02:00:42 PM UTC 25 | Feb 09 02:00:44 PM UTC 25 | 379996244 ps | ||
| T3 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.2520394381 | Feb 09 02:00:44 PM UTC 25 | Feb 09 02:00:47 PM UTC 25 | 91977387 ps | ||
| T11 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.770579637 | Feb 09 02:00:43 PM UTC 25 | Feb 09 02:00:47 PM UTC 25 | 395140794 ps | ||
| T18 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.1957687897 | Feb 09 02:00:41 PM UTC 25 | Feb 09 02:00:48 PM UTC 25 | 2783292447 ps | ||
| T4 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.2906493645 | Feb 09 02:00:46 PM UTC 25 | Feb 09 02:00:49 PM UTC 25 | 426053240 ps | ||
| T12 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.2323807387 | Feb 09 02:00:42 PM UTC 25 | Feb 09 02:00:49 PM UTC 25 | 934276066 ps | ||
| T45 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.476113179 | Feb 09 02:00:39 PM UTC 25 | Feb 09 02:00:49 PM UTC 25 | 6190205554 ps | ||
| T19 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.2854554902 | Feb 09 02:00:39 PM UTC 25 | Feb 09 02:00:49 PM UTC 25 | 4635346512 ps | ||
| T5 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.1882662302 | Feb 09 02:00:47 PM UTC 25 | Feb 09 02:00:50 PM UTC 25 | 280826941 ps | ||
| T42 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.2589069845 | Feb 09 02:00:48 PM UTC 25 | Feb 09 02:00:51 PM UTC 25 | 1048056537 ps | ||
| T37 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1062939061 | Feb 09 02:00:47 PM UTC 25 | Feb 09 02:00:52 PM UTC 25 | 929336636 ps | ||
| T43 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.2770777877 | Feb 09 02:00:45 PM UTC 25 | Feb 09 02:00:52 PM UTC 25 | 763663615 ps | ||
| T20 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.162907085 | Feb 09 02:00:49 PM UTC 25 | Feb 09 02:00:52 PM UTC 25 | 979778322 ps | ||
| T13 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.2386371965 | Feb 09 02:00:49 PM UTC 25 | Feb 09 02:00:52 PM UTC 25 | 389561778 ps | ||
| T6 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2434680628 | Feb 09 02:00:51 PM UTC 25 | Feb 09 02:00:53 PM UTC 25 | 150963954 ps | ||
| T23 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3276590068 | Feb 09 02:00:50 PM UTC 25 | Feb 09 02:00:53 PM UTC 25 | 127511798 ps | ||
| T7 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1009555032 | Feb 09 02:00:50 PM UTC 25 | Feb 09 02:00:54 PM UTC 25 | 545124266 ps | ||
| T47 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.2032060874 | Feb 09 02:00:52 PM UTC 25 | Feb 09 02:00:54 PM UTC 25 | 404868543 ps | ||
| T57 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.364935057 | Feb 09 02:00:52 PM UTC 25 | Feb 09 02:00:54 PM UTC 25 | 62411567 ps | ||
| T90 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.3217561356 | Feb 09 02:00:53 PM UTC 25 | Feb 09 02:00:55 PM UTC 25 | 117244982 ps | ||
| T73 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.2277188597 | Feb 09 02:00:53 PM UTC 25 | Feb 09 02:00:55 PM UTC 25 | 99142123 ps | ||
| T27 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.1518409067 | Feb 09 02:00:53 PM UTC 25 | Feb 09 02:00:55 PM UTC 25 | 73176313 ps | ||
| T53 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.1268122504 | Feb 09 02:00:53 PM UTC 25 | Feb 09 02:00:57 PM UTC 25 | 1015346948 ps | ||
| T68 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.1821280097 | Feb 09 02:00:55 PM UTC 25 | Feb 09 02:00:57 PM UTC 25 | 86661943 ps | ||
| T67 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.1323979866 | Feb 09 02:00:54 PM UTC 25 | Feb 09 02:00:58 PM UTC 25 | 545554016 ps | ||
| T41 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.864359495 | Feb 09 02:00:40 PM UTC 25 | Feb 09 02:01:40 PM UTC 25 | 8767431495 ps | ||
| T14 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1738851634 | Feb 09 02:00:50 PM UTC 25 | Feb 09 02:00:58 PM UTC 25 | 1052494536 ps | ||
| T92 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.3128957448 | Feb 09 02:00:55 PM UTC 25 | Feb 09 02:01:01 PM UTC 25 | 3022904208 ps | ||
| T46 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.4178806251 | Feb 09 02:00:57 PM UTC 25 | Feb 09 02:01:01 PM UTC 25 | 544177719 ps | ||
| T93 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2039586841 | Feb 09 02:00:39 PM UTC 25 | Feb 09 02:01:01 PM UTC 25 | 5098195096 ps | ||
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| T183 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.130796245 | Feb 09 02:03:10 PM UTC 25 | Feb 09 02:03:37 PM UTC 25 | 8752920931 ps | ||
| T194 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.2840637636 | Feb 09 02:03:25 PM UTC 25 | Feb 09 02:03:38 PM UTC 25 | 2340556868 ps | ||
| T34 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.2017632538 | Feb 09 02:03:30 PM UTC 25 | Feb 09 02:03:38 PM UTC 25 | 1474615629 ps | ||
| T29 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/48.rv_dm_stress_all.3012197703 | Feb 09 02:03:32 PM UTC 25 | Feb 09 02:03:38 PM UTC 25 | 3128788601 ps | ||
| T203 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.192712099 | Feb 09 02:03:03 PM UTC 25 | Feb 09 02:03:39 PM UTC 25 | 9087453274 ps | ||
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| T245 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.3978021474 | Feb 09 02:03:27 PM UTC 25 | Feb 09 02:03:40 PM UTC 25 | 5421890463 ps | ||
| T181 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.1154293556 | Feb 09 02:03:27 PM UTC 25 | Feb 09 02:03:42 PM UTC 25 | 2593173547 ps | ||
| T166 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/15.rv_dm_autoincr_sba_tl_access.3134957837 | Feb 09 02:02:39 PM UTC 25 | Feb 09 02:03:58 PM UTC 25 | 80666132609 ps | ||
| T154 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4278428303 | Feb 09 02:02:44 PM UTC 25 | Feb 09 02:05:11 PM UTC 25 | 40919613081 ps | ||
| T55 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.747640257 | Feb 09 02:01:52 PM UTC 25 | Feb 09 02:06:54 PM UTC 25 | 23515134543 ps | ||
| T49 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3339992464 | Feb 09 02:01:39 PM UTC 25 | Feb 09 02:08:29 PM UTC 25 | 249334044285 ps | ||
| T65 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.1740421300 | Feb 09 02:01:28 PM UTC 25 | Feb 09 02:08:44 PM UTC 25 | 41171131505 ps | ||
| T80 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.2301892413 | Feb 09 02:02:01 PM UTC 25 | Feb 09 02:15:09 PM UTC 25 | 199374540925 ps | ||
| T26 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/6.rv_dm_stress_all_with_rand_reset.2594217311 | Feb 09 02:01:45 PM UTC 25 | Feb 09 02:22:03 PM UTC 25 | 53708517989 ps | ||
| T81 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all_with_rand_reset.3404397557 | Feb 09 02:01:21 PM UTC 25 | Feb 09 02:22:46 PM UTC 25 | 340242949965 ps | ||
| T99 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.646708099 | Feb 09 02:01:57 PM UTC 25 | Feb 09 02:28:31 PM UTC 25 | 146712028924 ps | ||
| T100 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.2281939326 | Feb 09 02:01:09 PM UTC 25 | Feb 09 02:37:28 PM UTC 25 | 231035628928 ps | ||
| T101 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2176585677 | Feb 09 02:01:14 PM UTC 25 | Feb 09 02:41:47 PM UTC 25 | 322733636645 ps | ||
| T82 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3146942992 | Feb 09 01:56:45 PM UTC 25 | Feb 09 01:56:48 PM UTC 25 | 256665897 ps | ||
| T83 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.751789355 | Feb 09 01:56:45 PM UTC 25 | Feb 09 01:56:48 PM UTC 25 | 543071806 ps | ||
| T84 | /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2223713213 | Feb 09 01:56:46 PM UTC 25 | Feb 09 01:56:49 PM UTC 25 | 876803312 ps |
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