Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.20 96.64 90.52 92.10 93.33 90.44 98.74 62.63


Total tests in report: 470
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
57.99 57.99 85.94 85.94 56.86 56.86 52.35 52.35 46.67 46.67 67.08 67.08 92.98 92.98 4.08 4.08 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.59112776
67.98 9.99 87.18 1.24 65.49 8.63 55.37 3.01 53.33 6.67 73.10 6.02 94.03 1.05 47.37 43.29 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2819749502
74.68 6.70 90.43 3.26 71.29 5.80 73.87 18.50 64.00 10.67 78.94 5.84 95.70 1.68 48.55 1.18 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3591596300
78.06 3.38 90.54 0.10 75.25 3.96 89.45 15.58 66.67 2.67 79.29 0.35 96.02 0.31 49.21 0.66 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1210175528
81.15 3.09 92.45 1.91 81.05 5.80 90.82 1.37 74.67 8.00 82.65 3.36 96.12 0.10 50.26 1.05 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.642997972
82.24 1.09 92.66 0.21 82.46 1.41 91.10 0.28 78.67 4.00 83.36 0.71 96.12 0.00 51.32 1.05 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1916770217
83.10 0.86 93.43 0.78 83.88 1.41 92.94 1.84 80.00 1.33 83.89 0.53 96.12 0.00 51.45 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2637864355
83.87 0.76 93.49 0.05 85.01 1.13 93.60 0.66 80.00 0.00 84.25 0.35 96.12 0.00 54.61 3.16 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2143418191
84.47 0.60 94.05 0.57 85.86 0.85 93.64 0.05 81.33 1.33 85.13 0.88 96.12 0.00 55.13 0.53 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1698021664
85.06 0.59 94.83 0.78 87.13 1.27 93.64 0.00 81.33 0.00 86.55 1.42 96.12 0.00 55.79 0.66 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2816134843
85.51 0.45 94.98 0.16 87.27 0.14 93.64 0.00 84.00 2.67 86.73 0.18 96.12 0.00 55.79 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all_with_rand_reset.2607259863
85.92 0.42 95.35 0.36 87.84 0.57 93.64 0.00 85.33 1.33 87.26 0.53 96.12 0.00 55.92 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3994006258
86.30 0.38 95.35 0.00 87.84 0.00 93.64 0.00 88.00 2.67 87.26 0.00 96.12 0.00 55.92 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1712382388
86.63 0.32 95.35 0.00 87.84 0.00 95.90 2.26 88.00 0.00 87.26 0.00 96.12 0.00 55.92 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.21908632
86.87 0.24 95.35 0.00 87.98 0.14 95.90 0.00 89.33 1.33 87.26 0.00 96.33 0.21 55.92 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all_with_rand_reset.567859112
87.10 0.23 95.50 0.16 88.40 0.42 96.28 0.38 89.33 0.00 87.79 0.53 96.33 0.00 56.05 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.123195574
87.32 0.22 95.55 0.05 88.54 0.14 96.47 0.19 89.33 0.00 88.14 0.35 96.33 0.00 56.84 0.79 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.1068131495
87.51 0.19 95.55 0.00 88.54 0.00 96.47 0.00 90.67 1.33 88.14 0.00 96.33 0.00 56.84 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.619712428
87.70 0.19 95.55 0.00 88.54 0.00 96.47 0.00 92.00 1.33 88.14 0.00 96.33 0.00 56.84 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2863543884
87.89 0.19 95.55 0.00 88.54 0.00 96.47 0.00 93.33 1.33 88.14 0.00 96.33 0.00 56.84 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all_with_rand_reset.2436516784
88.06 0.17 95.55 0.00 88.54 0.00 96.75 0.28 93.33 0.00 88.14 0.00 96.33 0.00 57.76 0.92 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1492852321
88.23 0.17 95.86 0.31 89.11 0.57 96.89 0.14 93.33 0.00 88.32 0.18 96.33 0.00 57.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.37730167
88.38 0.15 95.86 0.00 89.11 0.00 96.89 0.00 93.33 0.00 88.32 0.00 97.38 1.05 57.76 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2456528865
88.53 0.15 96.12 0.26 89.11 0.00 97.03 0.14 93.33 0.00 88.67 0.35 97.38 0.00 58.03 0.26 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.476664209
88.66 0.14 96.43 0.31 89.39 0.28 97.03 0.00 93.33 0.00 89.03 0.35 97.38 0.00 58.03 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_stress_all_with_rand_reset.2119822898
88.77 0.11 96.48 0.05 89.67 0.28 97.03 0.00 93.33 0.00 89.20 0.18 97.38 0.00 58.29 0.26 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.274390158
88.88 0.11 96.54 0.05 89.82 0.14 97.22 0.19 93.33 0.00 89.56 0.35 97.38 0.00 58.29 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3425029598
88.97 0.09 96.54 0.00 89.82 0.00 97.22 0.00 93.33 0.00 89.56 0.00 97.38 0.00 58.95 0.66 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/40.rv_dm_stress_all.1000520638
89.06 0.09 96.54 0.00 89.82 0.00 97.22 0.00 93.33 0.00 89.56 0.00 98.01 0.63 58.95 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3249941230
89.15 0.09 96.54 0.00 89.96 0.14 97.22 0.00 93.33 0.00 89.91 0.35 98.01 0.00 59.08 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2428715139
89.22 0.08 96.54 0.00 89.96 0.00 97.22 0.00 93.33 0.00 89.91 0.00 98.01 0.00 59.61 0.53 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.90756656
89.29 0.06 96.54 0.00 90.10 0.14 97.22 0.00 93.33 0.00 90.09 0.18 98.01 0.00 59.74 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2495551992
89.35 0.06 96.54 0.00 90.10 0.00 97.22 0.00 93.33 0.00 90.09 0.00 98.01 0.00 60.13 0.39 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2592024801
89.40 0.06 96.54 0.00 90.10 0.00 97.22 0.00 93.33 0.00 90.09 0.00 98.01 0.00 60.53 0.39 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.2812556346
89.44 0.04 96.54 0.00 90.38 0.28 97.22 0.00 93.33 0.00 90.09 0.00 98.01 0.00 60.53 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.4209167188
89.48 0.04 96.54 0.00 90.52 0.14 97.22 0.00 93.33 0.00 90.09 0.00 98.01 0.00 60.66 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1193841208
89.52 0.04 96.54 0.00 90.52 0.00 97.22 0.00 93.33 0.00 90.09 0.00 98.01 0.00 60.92 0.26 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2159014742
89.56 0.04 96.54 0.00 90.52 0.00 97.22 0.00 93.33 0.00 90.09 0.00 98.01 0.00 61.18 0.26 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2496879580
89.59 0.04 96.54 0.00 90.52 0.00 97.22 0.00 93.33 0.00 90.09 0.00 98.01 0.00 61.45 0.26 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.246582610
89.63 0.03 96.59 0.05 90.52 0.00 97.22 0.00 93.33 0.00 90.27 0.18 98.01 0.00 61.45 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1334103136
89.66 0.03 96.64 0.05 90.52 0.00 97.22 0.00 93.33 0.00 90.44 0.18 98.01 0.00 61.45 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3948319646
89.69 0.03 96.64 0.00 90.52 0.00 97.22 0.00 93.33 0.00 90.44 0.00 98.22 0.21 61.45 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3558206780
89.72 0.03 96.64 0.00 90.52 0.00 97.22 0.00 93.33 0.00 90.44 0.00 98.43 0.21 61.45 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.990202596
89.74 0.03 96.64 0.00 90.52 0.00 97.27 0.05 93.33 0.00 90.44 0.00 98.43 0.00 61.58 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2959218755
89.76 0.02 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.43 0.00 61.71 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/12.rv_dm_tl_intg_err.519590747
89.78 0.02 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.43 0.00 61.84 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/17.rv_dm_tl_intg_err.535399975
89.80 0.02 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.43 0.00 61.97 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2753153097
89.82 0.02 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.43 0.00 62.11 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.773939087
89.84 0.02 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.43 0.00 62.24 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.840030457
89.86 0.02 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.43 0.00 62.37 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1755433740
89.88 0.02 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.43 0.00 62.50 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1485083626
89.90 0.02 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.43 0.00 62.63 0.13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3093226842
89.91 0.01 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.53 0.10 62.63 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/14.rv_dm_csr_rw.3577687786
89.93 0.01 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.64 0.10 62.63 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1088285414
89.94 0.01 96.64 0.00 90.52 0.00 97.27 0.00 93.33 0.00 90.44 0.00 98.74 0.10 62.63 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3786425985

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1603587181
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1235488627
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3339317547
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.709105668
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_csr_rw.3074771012
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3609537834
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3677488552
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2663165378
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2130636795
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3525402693
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1290968424
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_partial_access.817299692
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_mem_walk.1671511773
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3272206061
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/0.rv_dm_tl_errors.3270178079
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4253265537
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2669978042
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_csr_rw.3769516477
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1178503529
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3892310590
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.661003020
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1426532302
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3280825101
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.472560793
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.936321511
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3673622924
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3307801037
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_mem_walk.1730091770
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3986977431
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1616245494
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/1.rv_dm_tl_errors.1269480798
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.523985409
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_csr_rw.3350887711
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3014026283
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1670011276
/workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1317751206
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Total test records in report: 470
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_resuming.384678116 Oct 15 01:10:42 AM UTC 24 Oct 15 01:10:47 AM UTC 24 531338418 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_halt_resume.1193841208 Oct 15 01:10:44 AM UTC 24 Oct 15 01:10:47 AM UTC 24 1389126393 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_busy.4270499187 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:49 AM UTC 24 1072221836 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_buffered_enable.1152551129 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:49 AM UTC 24 213461288 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_alert_test.37730167 Oct 15 01:10:39 AM UTC 24 Oct 15 01:10:51 AM UTC 24 129834228 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sec_cm.1210175528 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:02 AM UTC 24 526687756 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.814221283 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 338867009 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_halt_resume_whereto.59112776 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:52 AM UTC 24 298783641 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1970802722 Oct 15 01:10:49 AM UTC 24 Oct 15 01:10:52 AM UTC 24 142811436 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_rom_read_access.3425029598 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 76569606 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_scanmode.1825237405 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 11159718 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_hartsel_warl.2435684641 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 205587455 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2632523855 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 123189309 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_busy.1615385179 Oct 15 01:10:40 AM UTC 24 Oct 15 01:10:52 AM UTC 24 603991154 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_dmi_failed_op.1698021664 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 188629202 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_debug_disabled.2521615319 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 155706521 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_mem_tl_access_halted.779774384 Oct 15 01:10:40 AM UTC 24 Oct 15 01:10:52 AM UTC 24 446657927 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_abstractcmd_status.715004498 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 444685516 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sparse_lc_gate_fsm.1088285414 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 109610847 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3987645635 Oct 15 01:10:49 AM UTC 24 Oct 15 01:10:52 AM UTC 24 426598935 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dtm_idle_hint.117406 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:52 AM UTC 24 425835247 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_ndmreset_req.476664209 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:53 AM UTC 24 519734748 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_progbuf_read_write_execute.2159014742 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:53 AM UTC 24 1000093061 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2207151132 Oct 15 01:10:51 AM UTC 24 Oct 15 01:10:53 AM UTC 24 182846717 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.985379588 Oct 15 01:10:37 AM UTC 24 Oct 15 01:10:53 AM UTC 24 497944546 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3112236404 Oct 15 01:10:51 AM UTC 24 Oct 15 01:10:53 AM UTC 24 261945329 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_exception.123195574 Oct 15 01:10:40 AM UTC 24 Oct 15 01:10:53 AM UTC 24 693029649 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_cmderr_not_supported.2777732271 Oct 15 01:10:40 AM UTC 24 Oct 15 01:10:53 AM UTC 24 703106435 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_dataaddr_rw_access.840030457 Oct 15 01:10:48 AM UTC 24 Oct 15 01:10:53 AM UTC 24 62715733 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_halt_resume_whereto.1736967979 Oct 15 01:10:48 AM UTC 24 Oct 15 01:10:54 AM UTC 24 245098634 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sec_cm.2422129332 Oct 15 01:10:39 AM UTC 24 Oct 15 01:10:54 AM UTC 24 446177975 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_hart_unavail.533816711 Oct 15 01:10:42 AM UTC 24 Oct 15 01:10:54 AM UTC 24 140815882 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_tl_access.2819771401 Oct 15 01:10:39 AM UTC 24 Oct 15 01:10:54 AM UTC 24 4436621589 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_abstractcmd_status.3104638600 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 121270250 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_tl_access.287897513 Oct 15 01:10:36 AM UTC 24 Oct 15 01:11:01 AM UTC 24 2141528586 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_hart_unavail.2765667742 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:00 AM UTC 24 117494163 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_progbuf_read_write_execute.1564407506 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 260474302 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_rom_read_access.2840956454 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 102031200 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_alert_test.3530809822 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:00 AM UTC 24 62278360 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_halt_resume_whereto.4185723493 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:00 AM UTC 24 272891333 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sec_cm.2834656089 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:03 AM UTC 24 2189389869 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_debug_disabled.521273299 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 34582283 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sparse_lc_gate_fsm.3786425985 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 60603226 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_alert_test.152000892 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 57745847 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_hart_unavail.386882211 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 128936445 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_buffered_enable.3520362638 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 207310227 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_stress_all.2217466220 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 1361956029 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_dmi_failed_op.3252022834 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:55 AM UTC 24 290351167 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_ndmreset_req.1944193657 Oct 15 01:10:49 AM UTC 24 Oct 15 01:10:55 AM UTC 24 687408522 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_halted.156579131 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:55 AM UTC 24 124394338 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_hart_unavail.2176324436 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:55 AM UTC 24 238689128 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_dataaddr_rw_access.201220640 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:55 AM UTC 24 83074525 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_not_supported.2753153097 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:56 AM UTC 24 197585996 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_exception.3674079712 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:56 AM UTC 24 146826710 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sec_cm.616204029 Oct 15 01:10:53 AM UTC 24 Oct 15 01:10:56 AM UTC 24 575250295 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_cmderr_halt_resume.1733146042 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:56 AM UTC 24 233905212 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_mem_tl_access_resuming.625261069 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:56 AM UTC 24 275774876 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_bad_sba_tl_access.3591596300 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:57 AM UTC 24 2129607256 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_sba_debug_disabled.2639070640 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:57 AM UTC 24 4712849788 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_bad_sba_tl_access.2158733534 Oct 15 01:10:40 AM UTC 24 Oct 15 01:10:58 AM UTC 24 2486823330 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_sba_debug_disabled.2495551992 Oct 15 01:10:49 AM UTC 24 Oct 15 01:10:58 AM UTC 24 4136834741 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_stress_all.642997972 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:04 AM UTC 24 4060481139 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_halt_resume_whereto.551391094 Oct 15 01:10:56 AM UTC 24 Oct 15 01:10:59 AM UTC 24 494627510 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_buffered_enable.3310241377 Oct 15 01:10:57 AM UTC 24 Oct 15 01:10:59 AM UTC 24 259047018 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sparse_lc_gate_fsm.3488339316 Oct 15 01:10:57 AM UTC 24 Oct 15 01:10:59 AM UTC 24 271167089 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_smoke.3939894861 Oct 15 01:10:36 AM UTC 24 Oct 15 01:10:59 AM UTC 24 3453604617 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2428715139 Oct 15 01:10:36 AM UTC 24 Oct 15 01:11:00 AM UTC 24 3983672610 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_alert_test.1227119379 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:00 AM UTC 24 177424976 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sparse_lc_gate_fsm.2689571136 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:00 AM UTC 24 89685130 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_buffered_enable.3994006258 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:00 AM UTC 24 274744541 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_alert_test.2195942884 Oct 15 01:10:59 AM UTC 24 Oct 15 01:11:01 AM UTC 24 68226601 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_hart_unavail.1973213598 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:01 AM UTC 24 164790707 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_bad_sba_tl_access.1276925422 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:01 AM UTC 24 596263719 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_halt_resume_whereto.2642188330 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:01 AM UTC 24 201587072 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_buffered_enable.3930726267 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:01 AM UTC 24 280957756 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_halt_resume_whereto.2182212838 Oct 15 01:10:59 AM UTC 24 Oct 15 01:11:01 AM UTC 24 627633581 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.413130397 Oct 15 01:10:39 AM UTC 24 Oct 15 01:11:01 AM UTC 24 9555398673 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_sec_cm.4040948270 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:01 AM UTC 24 614123445 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_tap_fsm.1916770217 Oct 15 01:10:36 AM UTC 24 Oct 15 01:11:04 AM UTC 24 7271411123 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_alert_test.2007251271 Oct 15 01:11:00 AM UTC 24 Oct 15 01:11:02 AM UTC 24 34796509 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.419622812 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:02 AM UTC 24 10349464007 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_buffered_enable.3721227144 Oct 15 01:10:59 AM UTC 24 Oct 15 01:11:02 AM UTC 24 746012603 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2865916164 Oct 15 01:10:59 AM UTC 24 Oct 15 01:11:02 AM UTC 24 2418775216 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_sba_tl_access.2468293739 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:03 AM UTC 24 2011369721 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_sba_tl_access.2969182360 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:03 AM UTC 24 4181295196 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.754222265 Oct 15 01:11:00 AM UTC 24 Oct 15 01:11:03 AM UTC 24 2272151506 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4122850759 Oct 15 01:10:53 AM UTC 24 Oct 15 01:11:03 AM UTC 24 10116558378 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/20.rv_dm_stress_all.3788268677 Oct 15 01:11:30 AM UTC 24 Oct 15 01:11:34 AM UTC 24 1203521239 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/6.rv_dm_sba_tl_access.1673875083 Oct 15 01:11:00 AM UTC 24 Oct 15 01:11:04 AM UTC 24 3074505485 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_sba_tl_access.4240549302 Oct 15 01:10:59 AM UTC 24 Oct 15 01:11:05 AM UTC 24 1938068586 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_sba_tl_access.3081093125 Oct 15 01:10:53 AM UTC 24 Oct 15 01:11:05 AM UTC 24 3192816632 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3339606754 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:05 AM UTC 24 4184455422 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_autoincr_sba_tl_access.2602867933 Oct 15 01:10:53 AM UTC 24 Oct 15 01:11:06 AM UTC 24 6662220790 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_stress_all.2816134843 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:07 AM UTC 24 2396691531 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_autoincr_sba_tl_access.472732675 Oct 15 01:10:36 AM UTC 24 Oct 15 01:11:07 AM UTC 24 14273964731 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all.773939087 Oct 15 01:10:39 AM UTC 24 Oct 15 01:11:08 AM UTC 24 5571258686 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_bad_sba_tl_access.3018320421 Oct 15 01:10:59 AM UTC 24 Oct 15 01:11:09 AM UTC 24 7649454633 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all.122467378 Oct 15 01:10:59 AM UTC 24 Oct 15 01:11:13 AM UTC 24 4062474315 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/2.rv_dm_bad_sba_tl_access.1765752033 Oct 15 01:10:53 AM UTC 24 Oct 15 01:11:14 AM UTC 24 12241516489 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_halt_resume_whereto.4209167188 Oct 15 01:11:02 AM UTC 24 Oct 15 01:11:17 AM UTC 24 395922010 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_buffered_enable.2186976933 Oct 15 01:11:02 AM UTC 24 Oct 15 01:11:18 AM UTC 24 345171836 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_bad_sba_tl_access.1492852321 Oct 15 01:11:02 AM UTC 24 Oct 15 01:11:19 AM UTC 24 4125794589 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_stress_all.3129892159 Oct 15 01:11:15 AM UTC 24 Oct 15 01:11:20 AM UTC 24 1633880572 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_alert_test.1533108554 Oct 15 01:11:10 AM UTC 24 Oct 15 01:11:21 AM UTC 24 71565480 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_alert_test.327599752 Oct 15 01:11:19 AM UTC 24 Oct 15 01:11:22 AM UTC 24 49544843 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_buffered_enable.1636244441 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:22 AM UTC 24 185812257 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_stress_all.3984858088 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:22 AM UTC 24 2677014175 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_sba_tl_access.2594239846 Oct 15 01:11:10 AM UTC 24 Oct 15 01:11:23 AM UTC 24 2099531625 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_autoincr_sba_tl_access.1068131495 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:24 AM UTC 24 2686846493 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_alert_test.758006160 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:24 AM UTC 24 71789446 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_autoincr_sba_tl_access.924763800 Oct 15 01:10:59 AM UTC 24 Oct 15 01:11:25 AM UTC 24 8640795409 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_alert_test.1003491334 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:25 AM UTC 24 38094959 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_alert_test.3983190736 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:25 AM UTC 24 30247450 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_alert_test.750091611 Oct 15 01:11:23 AM UTC 24 Oct 15 01:11:25 AM UTC 24 46796320 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_bad_sba_tl_access.246582610 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:26 AM UTC 24 1548208361 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_alert_test.3569512217 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:26 AM UTC 24 73334102 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1354681393 Oct 15 01:11:10 AM UTC 24 Oct 15 01:11:26 AM UTC 24 1941014703 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_sba_tl_access.752981797 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:26 AM UTC 24 444241761 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_sba_tl_access.1356405300 Oct 15 01:11:24 AM UTC 24 Oct 15 01:11:26 AM UTC 24 769391410 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_buffered_enable.4129240544 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:26 AM UTC 24 520003030 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_autoincr_sba_tl_access.1650360390 Oct 15 01:11:15 AM UTC 24 Oct 15 01:11:27 AM UTC 24 7875551987 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_alert_test.2110415374 Oct 15 01:11:24 AM UTC 24 Oct 15 01:11:27 AM UTC 24 46699824 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_alert_test.948813730 Oct 15 01:11:25 AM UTC 24 Oct 15 01:11:27 AM UTC 24 39805077 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_bad_sba_tl_access.895398608 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:27 AM UTC 24 811344037 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1982846854 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:27 AM UTC 24 2190164852 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1276841628 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:27 AM UTC 24 1437206353 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_sba_tl_access.1846008901 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:27 AM UTC 24 1367182967 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_stress_all.2421010551 Oct 15 01:11:23 AM UTC 24 Oct 15 01:11:27 AM UTC 24 1925304792 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/12.rv_dm_bad_sba_tl_access.1929518816 Oct 15 01:11:10 AM UTC 24 Oct 15 01:11:28 AM UTC 24 2528764517 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_bad_sba_tl_access.2040994536 Oct 15 01:11:20 AM UTC 24 Oct 15 01:11:28 AM UTC 24 1916281307 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_stress_all.3379840230 Oct 15 01:11:26 AM UTC 24 Oct 15 01:11:34 AM UTC 24 1365355469 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_bad_sba_tl_access.2387622138 Oct 15 01:11:24 AM UTC 24 Oct 15 01:11:28 AM UTC 24 1326504027 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all.2666624630 Oct 15 01:11:02 AM UTC 24 Oct 15 01:11:28 AM UTC 24 2179229116 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_bad_sba_tl_access.908836112 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:28 AM UTC 24 2867622475 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_alert_test.1951719138 Oct 15 01:11:26 AM UTC 24 Oct 15 01:11:29 AM UTC 24 127223126 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_stress_all.1812888776 Oct 15 01:11:23 AM UTC 24 Oct 15 01:11:29 AM UTC 24 1232646351 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_autoincr_sba_tl_access.4051567304 Oct 15 01:11:23 AM UTC 24 Oct 15 01:11:29 AM UTC 24 3726748178 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_stress_all.2961962288 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:29 AM UTC 24 881961584 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_alert_test.4152511508 Oct 15 01:11:28 AM UTC 24 Oct 15 01:11:30 AM UTC 24 103984095 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_sba_tl_access.3224141961 Oct 15 01:11:25 AM UTC 24 Oct 15 01:11:30 AM UTC 24 2905428321 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_bad_sba_tl_access.894260808 Oct 15 01:11:23 AM UTC 24 Oct 15 01:11:30 AM UTC 24 1299251675 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_stress_all.1755433740 Oct 15 01:11:25 AM UTC 24 Oct 15 01:11:30 AM UTC 24 3221466196 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_bad_sba_tl_access.3595684435 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:30 AM UTC 24 5957657930 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2834738477 Oct 15 01:11:23 AM UTC 24 Oct 15 01:11:31 AM UTC 24 2370208391 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.369304750 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:31 AM UTC 24 1960105990 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2311357191 Oct 15 01:11:27 AM UTC 24 Oct 15 01:11:31 AM UTC 24 2439240648 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_alert_test.464227181 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:31 AM UTC 24 56380631 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/11.rv_dm_sba_tl_access.2343403392 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:32 AM UTC 24 2683178473 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/20.rv_dm_alert_test.534316597 Oct 15 01:11:30 AM UTC 24 Oct 15 01:11:32 AM UTC 24 42706881 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_alert_test.741689492 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:32 AM UTC 24 111151214 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1059735643 Oct 15 01:11:19 AM UTC 24 Oct 15 01:11:32 AM UTC 24 3377899585 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1891891315 Oct 15 01:11:24 AM UTC 24 Oct 15 01:11:33 AM UTC 24 1848313420 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_bad_sba_tl_access.3181503759 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:33 AM UTC 24 13978155111 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all.2207125744 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:33 AM UTC 24 2692535381 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_sba_tl_access.1034192822 Oct 15 01:11:26 AM UTC 24 Oct 15 01:11:33 AM UTC 24 2646129923 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/21.rv_dm_alert_test.1998153916 Oct 15 01:11:31 AM UTC 24 Oct 15 01:11:33 AM UTC 24 61795859 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/22.rv_dm_alert_test.2207122629 Oct 15 01:11:31 AM UTC 24 Oct 15 01:11:33 AM UTC 24 190575491 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_stress_all.2959218755 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:34 AM UTC 24 1372091639 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/23.rv_dm_alert_test.3386738111 Oct 15 01:11:31 AM UTC 24 Oct 15 01:11:34 AM UTC 24 89857128 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3592304876 Oct 15 01:11:26 AM UTC 24 Oct 15 01:11:34 AM UTC 24 2961502440 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_stress_all.1382388834 Oct 15 01:11:28 AM UTC 24 Oct 15 01:11:34 AM UTC 24 5915998858 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3367789598 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:35 AM UTC 24 1401806914 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/17.rv_dm_autoincr_sba_tl_access.1962849841 Oct 15 01:11:28 AM UTC 24 Oct 15 01:11:35 AM UTC 24 4352294663 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_stress_all.1934725767 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:36 AM UTC 24 6213709341 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_sba_tl_access.3570167122 Oct 15 01:11:28 AM UTC 24 Oct 15 01:11:36 AM UTC 24 7619093082 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1295448509 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:37 AM UTC 24 10359946649 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/27.rv_dm_alert_test.3248824828 Oct 15 01:11:34 AM UTC 24 Oct 15 01:11:37 AM UTC 24 30689963 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/23.rv_dm_stress_all.2982591764 Oct 15 01:11:31 AM UTC 24 Oct 15 01:11:37 AM UTC 24 2512426406 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/29.rv_dm_alert_test.3580422687 Oct 15 01:11:34 AM UTC 24 Oct 15 01:11:37 AM UTC 24 29578293 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/30.rv_dm_alert_test.278190996 Oct 15 01:11:34 AM UTC 24 Oct 15 01:11:37 AM UTC 24 76801472 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/28.rv_dm_alert_test.3391414304 Oct 15 01:11:34 AM UTC 24 Oct 15 01:11:37 AM UTC 24 219772138 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/33.rv_dm_alert_test.1293227445 Oct 15 01:11:35 AM UTC 24 Oct 15 01:11:37 AM UTC 24 166107231 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/34.rv_dm_alert_test.262058397 Oct 15 01:11:35 AM UTC 24 Oct 15 01:11:37 AM UTC 24 95484567 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/42.rv_dm_stress_all.406163748 Oct 15 01:11:39 AM UTC 24 Oct 15 01:11:59 AM UTC 24 5657345952 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.659134955 Oct 15 01:11:28 AM UTC 24 Oct 15 01:11:37 AM UTC 24 2527700726 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/24.rv_dm_alert_test.2738588264 Oct 15 01:11:32 AM UTC 24 Oct 15 01:11:38 AM UTC 24 41922966 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/25.rv_dm_alert_test.3766901911 Oct 15 01:11:32 AM UTC 24 Oct 15 01:11:38 AM UTC 24 64969455 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/31.rv_dm_alert_test.1818940979 Oct 15 01:11:35 AM UTC 24 Oct 15 01:11:38 AM UTC 24 84929136 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/32.rv_dm_alert_test.3219127481 Oct 15 01:11:35 AM UTC 24 Oct 15 01:11:38 AM UTC 24 75190053 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/14.rv_dm_sba_tl_access.4119621833 Oct 15 01:11:23 AM UTC 24 Oct 15 01:11:38 AM UTC 24 7142762595 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/24.rv_dm_stress_all.4190222105 Oct 15 01:11:31 AM UTC 24 Oct 15 01:11:38 AM UTC 24 2207507676 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/26.rv_dm_alert_test.216719530 Oct 15 01:11:32 AM UTC 24 Oct 15 01:11:38 AM UTC 24 111041158 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/10.rv_dm_sba_tl_access.4232992294 Oct 15 01:11:06 AM UTC 24 Oct 15 01:11:39 AM UTC 24 9813051351 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/30.rv_dm_stress_all.274390158 Oct 15 01:11:34 AM UTC 24 Oct 15 01:11:39 AM UTC 24 3375868041 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/0.rv_dm_stress_all_with_rand_reset.2819749502 Oct 15 01:10:39 AM UTC 24 Oct 15 01:11:39 AM UTC 24 3181291052 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/3.rv_dm_autoincr_sba_tl_access.1227649374 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:39 AM UTC 24 51730757480 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/32.rv_dm_stress_all.3979592757 Oct 15 01:11:35 AM UTC 24 Oct 15 01:11:39 AM UTC 24 2066143043 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_stress_all.2496879580 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:40 AM UTC 24 3423643194 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/28.rv_dm_stress_all.1485083626 Oct 15 01:11:34 AM UTC 24 Oct 15 01:11:41 AM UTC 24 3118239900 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/4.rv_dm_autoincr_sba_tl_access.207599214 Oct 15 01:10:58 AM UTC 24 Oct 15 01:11:41 AM UTC 24 13548162778 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/44.rv_dm_alert_test.1951396548 Oct 15 01:11:40 AM UTC 24 Oct 15 01:11:41 AM UTC 24 106135746 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/45.rv_dm_alert_test.291175557 Oct 15 01:11:40 AM UTC 24 Oct 15 01:11:41 AM UTC 24 150104879 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/35.rv_dm_alert_test.413960948 Oct 15 01:11:37 AM UTC 24 Oct 15 01:11:42 AM UTC 24 33744533 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/27.rv_dm_stress_all.1511325186 Oct 15 01:11:32 AM UTC 24 Oct 15 01:11:42 AM UTC 24 1411688726 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_bad_sba_tl_access.328886484 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:42 AM UTC 24 7628126654 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/25.rv_dm_stress_all.1055661796 Oct 15 01:11:32 AM UTC 24 Oct 15 01:11:42 AM UTC 24 1462648977 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/43.rv_dm_alert_test.1576054536 Oct 15 01:11:39 AM UTC 24 Oct 15 01:11:42 AM UTC 24 42455053 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/22.rv_dm_stress_all.1172067305 Oct 15 01:11:31 AM UTC 24 Oct 15 01:11:43 AM UTC 24 7386017944 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/41.rv_dm_alert_test.279139338 Oct 15 01:11:39 AM UTC 24 Oct 15 01:11:43 AM UTC 24 80931483 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/34.rv_dm_stress_all.1349662841 Oct 15 01:11:35 AM UTC 24 Oct 15 01:11:43 AM UTC 24 2677750417 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/42.rv_dm_alert_test.2722718204 Oct 15 01:11:39 AM UTC 24 Oct 15 01:11:43 AM UTC 24 98318170 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/33.rv_dm_stress_all.2410548354 Oct 15 01:11:35 AM UTC 24 Oct 15 01:11:43 AM UTC 24 3197824114 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_autoincr_sba_tl_access.90756656 Oct 15 01:11:02 AM UTC 24 Oct 15 01:11:44 AM UTC 24 10002133916 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/45.rv_dm_stress_all.51518127 Oct 15 01:11:40 AM UTC 24 Oct 15 01:11:44 AM UTC 24 1682693128 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/43.rv_dm_stress_all.260190410 Oct 15 01:11:39 AM UTC 24 Oct 15 01:11:44 AM UTC 24 2316602676 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/5.rv_dm_stress_all_with_rand_reset.3948319646 Oct 15 01:11:00 AM UTC 24 Oct 15 01:11:44 AM UTC 24 26892037748 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/26.rv_dm_stress_all.3480439804 Oct 15 01:11:32 AM UTC 24 Oct 15 01:11:44 AM UTC 24 2343469870 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_autoincr_sba_tl_access.4134295651 Oct 15 01:11:26 AM UTC 24 Oct 15 01:11:45 AM UTC 24 4768726360 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_stress_all_with_rand_reset.1092462516 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:46 AM UTC 24 1616768203 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/36.rv_dm_alert_test.278506040 Oct 15 01:11:38 AM UTC 24 Oct 15 01:11:46 AM UTC 24 77964367 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/38.rv_dm_alert_test.2021527149 Oct 15 01:11:38 AM UTC 24 Oct 15 01:11:46 AM UTC 24 39059860 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/37.rv_dm_alert_test.2952832481 Oct 15 01:11:38 AM UTC 24 Oct 15 01:11:46 AM UTC 24 130386267 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/40.rv_dm_alert_test.18466663 Oct 15 01:11:38 AM UTC 24 Oct 15 01:11:46 AM UTC 24 158370739 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/39.rv_dm_alert_test.441108454 Oct 15 01:11:38 AM UTC 24 Oct 15 01:11:46 AM UTC 24 152540658 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_autoincr_sba_tl_access.21908632 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:47 AM UTC 24 18452645918 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/38.rv_dm_stress_all.1140804743 Oct 15 01:11:38 AM UTC 24 Oct 15 01:11:47 AM UTC 24 2314702452 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/21.rv_dm_stress_all.2576849231 Oct 15 01:11:31 AM UTC 24 Oct 15 01:12:01 AM UTC 24 8424422112 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/37.rv_dm_stress_all.2812556346 Oct 15 01:11:38 AM UTC 24 Oct 15 01:11:48 AM UTC 24 1547479261 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/46.rv_dm_stress_all.1437762200 Oct 15 01:11:41 AM UTC 24 Oct 15 01:11:48 AM UTC 24 3582805471 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/36.rv_dm_stress_all.3093226842 Oct 15 01:11:37 AM UTC 24 Oct 15 01:11:48 AM UTC 24 2312723549 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/16.rv_dm_bad_sba_tl_access.3989310296 Oct 15 01:11:26 AM UTC 24 Oct 15 01:11:49 AM UTC 24 6961649841 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/7.rv_dm_stress_all_with_rand_reset.2637864355 Oct 15 01:11:02 AM UTC 24 Oct 15 01:11:49 AM UTC 24 9455938520 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/13.rv_dm_sba_tl_access.2334215322 Oct 15 01:11:19 AM UTC 24 Oct 15 01:11:49 AM UTC 24 9097551731 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/44.rv_dm_stress_all.384329124 Oct 15 01:11:39 AM UTC 24 Oct 15 01:11:50 AM UTC 24 2787372605 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/47.rv_dm_stress_all.3022861183 Oct 15 01:11:41 AM UTC 24 Oct 15 01:11:50 AM UTC 24 4121261366 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/41.rv_dm_stress_all.1837361523 Oct 15 01:11:39 AM UTC 24 Oct 15 01:11:51 AM UTC 24 2973124925 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/18.rv_dm_bad_sba_tl_access.168458234 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:51 AM UTC 24 6373588759 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/19.rv_dm_sba_tl_access.1348595167 Oct 15 01:11:29 AM UTC 24 Oct 15 01:11:52 AM UTC 24 6485375093 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/8.rv_dm_autoincr_sba_tl_access.1338679405 Oct 15 01:11:03 AM UTC 24 Oct 15 01:11:52 AM UTC 24 21856515298 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/47.rv_dm_alert_test.3286596662 Oct 15 01:11:41 AM UTC 24 Oct 15 01:11:53 AM UTC 24 65477997 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/39.rv_dm_stress_all.512824415 Oct 15 01:11:38 AM UTC 24 Oct 15 01:11:53 AM UTC 24 2754013763 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/46.rv_dm_alert_test.832326198 Oct 15 01:11:41 AM UTC 24 Oct 15 01:11:53 AM UTC 24 128488439 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/coverage/default/48.rv_dm_alert_test.117376207 Oct 15 01:11:42 AM UTC 24 Oct 15 01:11:54 AM UTC 24 35878116 ps
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